參數(shù)資料
型號(hào)： MAX5898EGK+D
廠(chǎng)商： Maxim Integrated Products
文件頁(yè)數(shù)： 9/33頁(yè)
文件大?。?/td> 0K
描述： IC DAC 16BIT DUAL 500MSPS 68-QFN
產(chǎn)品培訓(xùn)模塊： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝： 30
設(shè)置時(shí)間： 11ns
位數(shù)： 16
數(shù)據(jù)接口： 并聯(lián)
轉(zhuǎn)換器數(shù)目： 2
電壓電源： 模擬和數(shù)字
功率耗散（最大）： 831mW
工作溫度： -40°C ~ 85°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 68-VFQFN 裸露焊盤(pán)
供應(yīng)商設(shè)備封裝： 68-QFN 裸露焊盤(pán)（10x10）
包裝： 管件
輸出數(shù)目和類(lèi)型： 2 電流，單極
采樣率（每秒）： 500M
MAX5898
16-Bit, 500Msps, Interpolating and Modulating
Dual DAC with Interleaved LVDS Inputs
______________________________________________________________________________________
17
Address 07h
Bit 7
Logic 0 (default) adds the 10 bits offset cur-
rent to OUTIN. A logic 1 adds the 10 bits off-
set current to OUTIP.
Address 08h
Bits 7–0
These 8 bits define the binary number for
fine-gain adjustment of the QDAC full-scale
current (see the
Gain Adjustment section). Bit
7 is the MSB. Default is all zeros.
Address 09h
Bits 3–0
These four bits define the binary number for
the coarse-gain adjustment of the QDAC full-
scale current (see the
Gain Adjustment sec-
tion). Bit 3 is the MSB. Default is all ones.
Address 0Ah, Bits 7–0; Address 0Bh, Bit 1 and Bit 0
These 10 bits represent a binary number that
defines the magnitude of the offset added to
the QDAC output (see the
Offset Adjustment
section). Default is all zeros.
Address 0Bh
Bit 7
Logic 0 (default) adds the 10 bits offset to
OUTQN. A logic 1 adds the 10 bits offset to
OUTQP.
Offset Adjustment
Offset adjustment is achieved by adding a digital code to
the DAC inputs. The code OFFSET (see equation below),
as stored in the relevant control registers, has a range
from 0 to 1023 and a sign bit. The applied DAC offset
is four times the code stored in the register, providing an
offset adjustment range of ±4092 LSB codes. The resolu-
tion is 4 LSB.
Gain Trim
Gain adjustment is peformed by varying the full-scale
current according to the following formula:
where IREF is the reference current (see the Reference
Input/Output section). COARSE is the register content
of registers 05h and 09h for the I and Q channel,
respectively. FINE is the register content of register 04h
and 08h for the I and Q channel, respectively. The
range of COARSE is from 0 to 15, with 15 being the
default. The range for FINE is from 0 to 255 with 0
being the default. The gain can be adjusted in steps of
approximately 0.01dB.
Data Input Port
The MAX5898 captures input data on a single LVDS
port (D15P/N–D0P/N). The channel for the input data is
determined through the state of SELIQP/SELIQN. When
SELIQP is set to logic-high and SELIQN is set to logic-
low the input data is presented to the I channel. Setting
SELIQP to logic-low and SELIQN to logic-high presents
the input data to the Q channel.
The MAX5898 control registers can be programmed to
allow either signed or unsigned binary format (bit 7,
address 02h) data. Table 3 shows the corresponding DAC
output levels when using signed or unsigned data modes.
Data Synchronization Modes
Data synchronization circuitry is provided to allow oper-
ation with an input data clock. The data clock must be
frequency locked to the DAC clock (fDAC), but can
have arbitrary phase with respect to the DAC clock.
The synchronization circuitry allows for phase jitter on
the input data clock of up to ±1 data clock cycles.
Synchronization is initially established when the reset
pin is asynchronously deasserted and the input data
clock has been running for at least four clock cycles.
Subsequently, the MAX5898 monitors the phase rela-
tionship and detects if the phase drifts more than ±1
data clock cycle. If this occurs, the synchronizer auto-
matically re-establishes synchronization. However, dur-
ing the resynchronization phase, up to 8 data words
may be lost or repeated.
Bit 2 of register 02h disables or enables (default) the
automatic data clock phase detection. Disabling the
data synchronization circuitry requires the data clock
and the DAC clock phase to be locked.
I
COARSE
I
FINE
OUTFS
REF
=
×
+
×
3
4
1
16
3
32
256
1024
24
I
OFFSET
I
OFFSET
OUTFS
=
×
4
2
16
DIGITAL INPUT CODE
OFFSET
BINARY
(UNSIGNED)
TWO'S
COMPLEMENT
(SIGNED)
OUT_POUT_N
0000 0000 0000 0000 1000 0000 0000 0000
0
IOUTFS
0111 1111 1111 1111 0000 0000 0000 0000
IOUTFS /
2
IOUTFS /
2
1111 1111 1111 1111 0111 1111 1111 1111
IOUTFS
0
Table 3. DAC Output Code Table
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