參數(shù)資料
型號: MAX2986CXV
廠商: Maxim Integrated Products, Inc.
英文描述: Single Channel M-LVDS Type-1 Receiver 8-SON
中文描述: 集成電力線數(shù)字收發(fā)器
文件頁數(shù): 20/28頁
文件大小: 349K
代理商: MAX2986CXV
M
Integrated Powerline Digital Transceiver
20
______________________________________________________________________________________
Table 16. MAX2986 to AFE Signal Interface Description
NAME
DATA
LINES
I/O
DESCRIPTION
AFETXEN
1
O
AFE Transmit Enable.
The AFETXEN signal is used to enable the transmitter of the AFE.
When AFETXEN and AFEREN are high, data is sent through the AFEDAD[9:0] to the DAC
and then into the powerline.
AFEREN
1
O
Setting Bus Direction.
The AFEREN signal sets the direction of the data bus
AFEDAD[9:0]. When high, data can be sent from the MAX2986 to the DAC in the AFE,
and when low, data is sent from the ADC to the MAX2986.
AFEPDRX
1
O
AFE Receiver Power-Down.
When the AFE is in transmit mode, the AFEPDRX signal
goes high, the receiver section of the AFE is powered down. The MAX2980 features a
transmit power-saving mode that reduces current dissipation. To use this power-saving
mode, lower AFEPDRX prior to the end of a transmission. If this mode is not required,
connect AFEPDRX to AFETXEN and AFEREN.
AFEDAD[9:0]
10
I/O
AFE 10-Bit ADC and DAC Bus.
AFEDAD[9:0] is the 10-bit bidirectional bus that
connects the MAX2986 to the AFE DAC and ADC. The direction of the bus is controlled
by AFEREN described above.
AFEFRZ
1
O
AFE Receive AGC Control.
The AFEFRZ signal controls the AGC circuit in the receive
path in the AFE. When this signal is low, the gain circuit on the input signal continuously
adapts for maximum sensitivity. This signal is raised high when the MAX2986 detects a
valid preamble. After the AFEFRZ signal is raised high, it continues to adapt for an
additional short period of time, then it locks the currently adapted level on the incoming
signal. The MAX2986 holds AFEFRZ high while receiving a transmission, and then lowers
for continuous adaptation for maximum sensitivity of other incoming signals.
AFECLK
1
O
AFE Clock.
A 50MHz clock generated for the MAX2980 AFE.
AFERESET
1
O
A F E R e s e
To p er or m a r eset on the M AX 2980 AFE AFE C LK m ust b e fr ee r unni ng and
AFE RE S E T m ust b e LO W for typ cal y 1s. A r eset m ust b e p er or m ed at p ow er up
GPIO[6]
GPIO[5]
GPIO[4]
GPIO[7]
1
1
1
1
O
I/O
O
O
AFE Serial Interface Read/Write Select.
AFE Serial Interface Data (Write/Read).
AFE Serial Interface Clock.
AFE Power-Down.
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