參數(shù)資料
型號(hào): MAX2986CXV
廠商: Maxim Integrated Products, Inc.
英文描述: Single Channel M-LVDS Type-1 Receiver 8-SON
中文描述: 集成電力線數(shù)字收發(fā)器
文件頁數(shù): 19/28頁
文件大小: 349K
代理商: MAX2986CXV
M
Integrated Powerline Digital Transceiver
______________________________________________________________________________________
19
Interfacing the MAX2986 to the
MAX2980 Analog Front End (AFE)
The interface to the MAX2980 AFE chip uses a bidirec-
tional bus to pass the digital data to and from the DAC
and ADC. Handshake lines help accomplish the data
transfer as well as operation of the AFE. Figure 22
shows the interface signals. For AFE pin configuration/
description, refer to the MAX2980 data sheet.
Table 15. Disabling UART
LOCATION
UARTTXD
UARTRXD
NAME
K7
L6
DIRECTION
O
I
TERMINATE STATUS
N.C.
V
DD
Table 14. Disabling MII/RMII/FIFO Interface
LOCATION
K11
F11
N10
J12
K12
J13
L12
N11
N12
N13
L13
L11
H10
H12
H11
H13
J11
K13
NAME
MIICRS
MIITXEN
MIICLK
MIIDAT[7]
MIIDAT[6]
MIIDAT[5]
MIIDAT[4]
MIIDAT[3]
MIIDAT[2]
MIIDAT[1]
MIIDAT[0]
MIIRXER
MIIRXDV
BUFCS
BUFRD
BUFWR
MIIMDC
MIIMDIO
DIRECTION
O
I
I
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
O
I
I
I
I
I/O
TERMINATE STATUS
N.C.
DGND
DGND
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
V
DD
V
DD
V
DD
DGND
N.C.
Note:
Disabling the UART interface disables the MAC code update and FLASH programming features of the chip.
AFEDAT[9:0]
AFEREN
AFETXEN
AFEPDRX
AFEFRZ
AFECLK
AFERESET
GPIO[7]
GPIO[4]
GPIO[5]
GPIO[6]
ADC/DAC
ENREAD
ENTX
SHRCRV
AFE
MAX2980
BASEBAND
MAX2986
CS
CLK
SI CLOCK
R/W SERIAL DATA
SERIAL R/W SELECT
SHDN
SCLK
SDI/O
SWR
RESETIN
Figure 22. MAX2980 AFE Interface to the MAX2986
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