參數(shù)資料
型號: MAX2986CXV
廠商: Maxim Integrated Products, Inc.
英文描述: Single Channel M-LVDS Type-1 Receiver 8-SON
中文描述: 集成電力線數(shù)字收發(fā)器
文件頁數(shù): 15/28頁
文件大?。?/td> 349K
代理商: MAX2986CXV
M
Integrated Powerline Digital Transceiver
______________________________________________________________________________________
15
FIFO Signal Timing—Receiving
When a frame is ready to send from the MAX2986 to
the external host, the MAX2986 asserts MIIRXDV after
an IFG (which is about 0.96μs), while there is no trans-
mission session in progress (with respect to MIICRS). A
receive process cannot start while a transmission is in
progress.
While the MAX2986 keeps MIIRXDV high, it sends 1
byte of data on MIIDAT for each positive edge on
BUFRD
. The first 2 bytes represent frame length in
MSB-first format. After the last byte of data is received,
the MAX2986 resets MIIRXDV. The direction of bidirec-
tional data pins is controlled through
BUFCS
and
BUFRD
pins. The MAX2986 enables data output drivers
when BUFCS = 0 and BUFRD = 0. The interactions
between the external host and the MAX2986 baseband
is shown in Figure 13 and the overall receive timing of
the buffering interface is illustrated in Figure 14, with
details in Figure 15 and Table 8.
READ LENGTH
(LSB)
READ FROM
FIFO INTERFACE
READ LENGTH
(MSB)
MIIRXDV
START
COUNTER =
FRAME LENGTH
YES
NO
'1'
'0'
Figure 13. Buffering (FIFO) Interface Receive Process from the
External Host View
DATA
DATA
DATA
DATA
FRAME LENGTH
(MSB)
FRAME LENGTH
(LSB)
MIIRXDV
MIIDAT
BUFRD
Figure 14. Receive Timing of the Buffering (FIFO) Interface
t
OV
t
OH
BUFRD
MIIDAT
MIIRXDV
MIICRS
Figure 15. FIFO Interface—Detailed Receive Timing
Table 8. FIFO Interface—Receive Timing*
PARAMETER
DESCRIPTION
MIN
UNITS
t
OV
Valid after negative
edge of
BUFRD
Debounce**
MIICLK
+ 3
ns
t
OH
Hold after positive
edge of
BUFRD
0
ns
*
Per IEEE 802.3u standard.
**
The default value of the debounce parameter is 3.
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