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參數(shù)資料
| 型號： | MAX2986CXV |
| 廠商： | Maxim Integrated Products, Inc. |
| 英文描述： | Single Channel M-LVDS Type-1 Receiver 8-SON |
| 中文描述： | 集成電力線數(shù)字收發(fā)器 |
| 文件頁數(shù)： | 14/28頁 |
| 文件大?。?/td> | 349K |
| 代理商： | MAX2986CXV |
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M
Integrated Powerline Digital Transceiver
14
______________________________________________________________________________________
FIFO Signal Timing—Transmitting
When the external host is ready to transmit a frame and
MIICRS is low (the previous transmission is finished), it
asserts MIITXEN. The external host must assert MIITXEN
if MIIRXDV is not high to avoid data loss. In response,
MIICRS is asserted by the MAX2986. While the external
host keeps MIITXEN high, 1 byte of data is transmitted
into the MAX2986 through MIIDAT for each positive
edge of
BUFWR
. After transmission of the last byte of
data, the external host resets MIITXEN. Interactions
between the external host and the MAX2986 baseband
chip are shown in Figure 10.
The overall transmission timing of the FIFO interface is
illustrated in Figure 11 with detailed timing shown in
Figure 12 and Table 7.
WRITE TO THE
FIFO
INTERFACE
RESET
MIITXEN
ASSERT
MIITXEN
FRAME
AVAILABLE
START
COUNTER =
FRAME LENGTH
YES
NO
YES
NO
CRS OR
RXDV
0
1
Figure 10. Buffering Transmission Process from the External
Host View
MIICRS
MIIDAT
MIITXEN
BUFWR
DATA
DATA
DATA
DATA
DATA
Figure 11. Transmission Timing of the Buffering (FIFO) Interface
MIIDAT
MIITXEN
t
IH
t
IS
BUFWR
Figure 12. FIFO Interface—Detailed Transmit Timing
Table 7. FIFO Interface—Transmit Timing*
PARAMETER
DESCRIPTION
TYP
UNITS
t
IS
Setup prior to positive
edge of
BUFWR
3
ns
t
IH
Hold after positive
edge of
BUFWR
Debounce**
MIICLK
+ 3
ns
*
Per IEEE 802.3u standard.
**
The default value of the debounce parameter is 3.
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相關(guān)代理商/技術(shù)參數(shù) |
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| MAX2986DVKIT | 制造商:Maxim Integrated Products 功能描述:PLDC (HOMEPLUG 1.0) BASEBAND W/O MAC - Rail/Tube |
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| MAX2986EVKIT+ | 制造商:Maxim Integrated Products 功能描述:EVAL KIT - Bulk |
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