參數(shù)資料
型號: MAX2986CXV
廠商: Maxim Integrated Products, Inc.
英文描述: Single Channel M-LVDS Type-1 Receiver 8-SON
中文描述: 集成電力線數(shù)字收發(fā)器
文件頁數(shù): 12/28頁
文件大小: 349K
代理商: MAX2986CXV
M
Integrated Powerline Digital Transceiver
12
______________________________________________________________________________________
Reduced Media
Independent Interface (rMII)
Table 5 describes the signals that provide data, status,
and control to the MAX2986 in RMII mode. In this
mode, data is transmitted and received in bit pairs. The
rMII mode connections are shown in Figure 9.
Table 5. rMII Signal Description
In case of an error in the received data, to eliminate the
requirement for MIIRXER and still meet the requirement
for undetected error rate, MIIDAT[5:4] replaces the
decoded data in the receive stream with 10 until the end
of carrier activity. By this replacement, the CRC check is
guaranteed to detect an error and reject the packet.
NAME
DATA
LINES
I/O
DESCRIPTION
MIIDAT[1:0]
2
I
Transmit Data.
Data are transferred to the interface from the external MAC across these two
lines, one di-bit at a time. MIIDAT[1:0] is 00 to indicate idle when MIITXEN is deasserted.
MIITXEN
1
I
Transmit Enable.
This signal indicates to the MAX2986 that valid data is present on the MIIDAT
pins. MIITXEN is asserted synchronously with the first nibble of the preamble and remains
asserted while all di-bits to be transmitted are presented to the rMII.
MIIDAT[5:4]
2
O
MII Receive Data.
Data is transferred from the MAX2986 to the external MAC across these two
lines, one di-bit at a time. Upon assertion of MIIRXDV, the MAX2986 ensures that MIIDAT[5:4] =
00 until proper receive decoding takes place.
MIIRXDV
1
O
Receive Data Valid (CRS_DV).
When asserted high, MIIRXDV indicates that the incoming data
on the MIIDAT pins are valid.
MIICLK
1
I
rMII Reference Clock.
A continuous clock that provides the timing reference for MIIRXDV,
MIIDAT, MIITXEN, and MIIRXER. MIICLK is sourced by the Ethernet MAC or an external source
and its frequency is 5MHz (50MHz) in 10Mbps (100Mbps) data rate.
MANAGEMENT DATA UNIT
MIIMDC
1
I
MII Management Data Clock.
A 2.5MHz noncontinuous clock reference for the MIIMDIO signal.
MIIMDIO
1
I/O
MII Management Data Input/Output.
It is a bidirectional signal that carries the data for the
management data interface.
REFCLK
CLOCK SOURCE (5MHz OR 50MHz)
TXEN
CRS_DV
TXD[1:0]
RXD[1:0]
MDC
MDIO
MIITXEN
MIICLK
MIIRXDV
MIIDAT[1:0]
MIIDAT[5:4]
MIIMDC
MIIMDIO
BUFWR
BUFRD
BUFCS
V
CC
ETHERNET
802.3 MAC
(RMII)
rMII
INTERFACE
MAC
MAX2986
PHY
Figure 9. MAC-PHY Connection in RMII Mode
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