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參數(shù)資料
| 型號： | MAX2986CXV |
| 廠商： | Maxim Integrated Products, Inc. |
| 英文描述： | Single Channel M-LVDS Type-1 Receiver 8-SON |
| 中文描述： | 集成電力線數(shù)字收發(fā)器 |
| 文件頁數(shù)： | 10/28頁 |
| 文件大?。?/td> | 349K |
| 代理商： | MAX2986CXV |
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M
Integrated Powerline Digital Transceiver
10
______________________________________________________________________________________
MII Signal Timing—Transmitting
When a frame in the external host is ready to transmit
and MIICRS is not high (the previous transmission has
finished), the external host asserts MIITXEN, while data
is ready on MIIDAT[3:0]. In response, the MAX2986
asserts MIICRS.
While the external host keeps MIITXEN high, data is
sampled synchronously with respect to MIICLK into the
MAX2986 through MIIDAT.
After transmission of the last byte of data and before
the next positive edge of the MIICLK, MIITXEN is reset
by the external host.
The transmission timing of the MII interface is illustrated
in Figure 5, with details in Figure 6 and Table 3.
DATA
DATA
DATA
DATA
MIICRS
MIIDAT
MIITXEN
MIICLK
Figure 5. Transmission Behavior of the MII Interface
MIIDAT
MIITXEN
MIICLK
t
IH
t
IS
Figure 6. MII Interface—Detailed Transmit Timing
Table 3. MII Interface—Detailed Transmit
Timing*
PARAMETER
DESCRIPTION
MIN
UNITS
t
IS
Setup prior to positive
edge of MIICLK
2.5
ns
t
IH
Hold after positive edge
of MIICLK
2.5
ns
*
Per IEEE 802.3u standard.
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