參數(shù)資料
型號: MAX11043ATL+T
廠商: Maxim Integrated Products
文件頁數(shù): 23/33頁
文件大?。?/td> 0K
描述: IC ADC 16BIT W/DAC 40-TQFN-EP
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝: 2,500
類型: ADC,DAC
分辨率(位): 16 b
采樣率(每秒): 9.6M
數(shù)據(jù)接口: 串行
電壓電源: 模擬和數(shù)字
電源電壓: 3 V ~ 3.6 V
工作溫度: -40°C ~ 125°C
安裝類型: 表面貼裝
封裝/外殼: 40-WFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 40-TQFN-EP(6x6)
包裝: 帶卷 (TR)
MAX11043
4-Channel, 16-Bit, Simultaneous-Sampling ADCs
with PGA, Filter, and 8-/12-Bit Dual-Stage DAC
3
Maxim Integrated
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DYNAMIC PERFORMANCE (PGA Enabled, PGA Gain = 8 x (25kHz -1dB Full-Scale Signal))
Maximum Full-Scale Input
ADC modulator gain = 1
150
mVP-P
Input-Referred Noise Spectral
Density
100kHz
20
nV/√Hz
Second Harmonic to
Fundamental
-92
dB
Third Harmonic to Fundamental
-94
dB
Spurious-Free Dynamic Range
SFDR
92
dB
Channel-to-Channel Isolation
Unused channels are shorted and
unconnected
110
dB
Channel Phase Matching
Between all channels, including complete
analog signal path
-0.05
+0.05
Degrees
DYNAMIC PERFORMANCE (PGA Enabled, PGA Gain = 16 x (25kHz -1dB Full-Scale Signal))
Maximum Full-Scale Input
ADC modulator gain = 1
75
mVP-P
Input-Referred Noise Spectral
Density
100kHz
15
nV/√Hz
Second Harmonic to
Fundamental
-99
dB
Third Harmonic to Fundamental
-93
dB
Spurious-Free Dynamic Range
SFDR
93
dB
Channel-to-Channel Isolation
Unused channels are shorted and
unconnected
106
dB
Channel Phase Matching
Between all channels, including complete
analog signal path
-0.075
+0.075
Degrees
DYNAMIC PERFORMANCE (EQ Mode (5kHz -1dB Full-Scale Signal, CONFIG_ Register Bit 3 = 1))
Maximum Full-Scale Input
ADC modulator gain = 1 (Note 2)
800
mVP-P
Input-Referred Noise Spectral
Density
100kHz
6
nV/√Hz
Second Harmonic to
Fundamental
-80
-90
dB
Third Harmonic to Fundamental
-77
-98
dB
Spurious-Free Dynamic Range
SFDR
Input referred (Note 3)
77
89
dB
ELECTRICAL CHARACTERISTICS (continued)
(VAVDD = +3.0V to +3.6V, VDVDD = +3.0V, CDVREG = 10F, VAGND = VDGND = 0V, common-mode input voltage = VAVDD/2, VREFBP
= VREFA = VREFB = VREFC = VREFD = +2.5V (external reference), VREFDAC = VREFDACH = +1.25V (external reference), VREFDACL =
0V, CREFBP = CREFA = CREFB = CREFC = CREFD = CREFDAC = 1F, fSCLK = 38.4MHz, fEXCLK = 38.4MHz (external clock applied to
OSCIN), clock divider set to 4, SHDN = DACSTEP = UP/DWN = DGND, CONVRUN = DVDD, all analog inputs driven directly through
a series 150
/330pF anti-alias filter, PGA gain = 1. Default filters and gain settings. DIFF = 1. TA = TMIN to TMAX, unless otherwise noted
(Note 1). Typical values are at TA = +25°C.)
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