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參數(shù)資料
| 型號： | MAX11043ATL+T |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 20/33頁 |
| 文件大小： | 0K |
| 描述： | IC ADC 16BIT W/DAC 40-TQFN-EP |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 類型： | ADC，DAC |
| 分辨率（位）： | 16 b |
| 采樣率（每秒）： | 9.6M |
| 數(shù)據(jù)接口： | 串行 |
| 電壓電源： | 模擬和數(shù)字 |
| 電源電壓： | 3 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 40-WFQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 40-TQFN-EP（6x6） |
| 包裝： | 帶卷 (TR) |
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MAX11043
4-Channel, 16-Bit, Simultaneous-Sampling ADCs
with PGA, Filter, and 8-/12-Bit Dual-Stage DAC
27
Maxim Integrated
C-RAM
ADDRESS
FLASH
ADDRESS
MSB FOR C-RAM
LSB FOR C-RAM
2Eh
—
EQ filter coefficient B3 and rectify bit for filter stage 7
17h
2Fh
EQ filter coefficient B2 for filter stage 7
—
30h
—
Not used
18h
31h*
ADC gain trim for gain = 1
—
32h
—
Not used
19h
33h*
ADC gain trim for gain = 2
—
34h
—
Not used
1Ah
35h*
ADC gain trim for gain = 4
—
36h
—
Not used
1Bh
37h*
EQ gain trim for gain = 2
—
38h
—
Not used
1Ch
39h*
EQ gain trim for gain = 4
—
3Ah*
—
LP filter gain for filter stage 1, gain = 1, 2, or 4
1Dh
3Bh*
LP filter coefficient -A2 for filter stage 1,
gain = 1, 2, or 4
—
3Ch
—
Not used
1Eh
3Dh*
LP filter coefficient -A3 for filter stage 1,
gain = 1, 2, or 4
—
3Eh*
—
LP filter coefficient B3 and rectify bit for filter stage 1,
gain = 1, 2, or 4
1Fh
3Fh*
LP filter coefficient B2 for filter stage 1,
gain = 1, 2, or 4
—
40h
—
Not used
20h
41h*
ADC gain trim for gain = 16
—
42h
—
Not used
21h
43h
User trim for ADC gain, default = 2000h
—
44h
—
Not used
22h
45h
Not used
—
46h*
—
LP filter gain for filter stage 1, gain = 16
23h
47h*
LP filter coefficient -A2 for filter stage 1,
gain = 16
—
48h
—
Not used
24h
49h*
LP filter coefficient -A3 for filter stage 1,
gain = 16
—
4Ah*
—
LP filter coefficient B3 and rectify bit for filter stage 1,
gain = 16
25h
4Bh*
LP filter coefficient B2 for filter stage 1,
gain = 16
—
4Ch
—
LP filter gain for filter stage 2
26h
4Dh
LP filter coefficient -A2 for filter stage 2
—
Table 4. C-RAM and Flash Memory Map (continued)
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