參數(shù)資料
型號： MAX11043ATL+T
廠商： Maxim Integrated Products
文件頁數(shù)： 11/33頁
文件大?。?/td> 0K
描述： IC ADC 16BIT W/DAC 40-TQFN-EP
產(chǎn)品培訓模塊： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝： 2,500
類型： ADC，DAC
分辨率（位）： 16 b
采樣率（每秒）： 9.6M
數(shù)據(jù)接口： 串行
電壓電源： 模擬和數(shù)字
電源電壓： 3 V ~ 3.6 V
工作溫度： -40°C ~ 125°C
安裝類型： 表面貼裝
封裝/外殼： 40-WFQFN 裸露焊盤
供應商設備封裝： 40-TQFN-EP（6x6）
包裝： 帶卷 (TR)
MAX11043
4-Channel, 16-Bit, Simultaneous-Sampling ADCs
with PGA, Filter, and 8-/12-Bit Dual-Stage DAC
19
Maxim Integrated
Register Functions
ADCA, ADCB, ADCC, and ADCD
Result Registers (00h–03h)
The ADC channel A, B, C, and D result registers pro-
vide the result data from the 4 ADC channels. EOC
asserts low when new data is available. Initiate a data
read prior to the next rising edge of EOC or the result is
overwritten. Set bit 5 of the configuration register 08h
high to read the data out in 24-bit resolution or set bit 5
low to read the data out in 16-bit resolution.
ADCAB, ADCCD, and ADCABCD
Result Registers (04h–06h)
Registers ADCAB, ADCCD, and ADCABCD contain
concatenated ADC results ensuring simultaneous
results are read. This reduces the risk of reading sam-
ples delayed by one cycle from channel to channel.
Set bit 5 of the configuration register 08h high to read
the data out in 24-bit resolution or set bit 5 low to read
the data out in 16-bit resolution.
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
X
Flash Busy
BOOT
OFLGA
OFLGB
OFLGC
OFLGD
Status Register (07h)
The status register contains the channel overflow flags
and POR bits.
X<7:6>: Don’t-care bits.
Flash Busy<5>: Do not start a new flash operation until
this is 0.
BOOT<4>: Power-on reset flag.
OFLG_<3:0>: Channel overflow flag, one per channel.
BIT 15
BIT 14
BIT 13
BIT 12
BIT 11
BIT 10
BIT 9
BIT 8
EXTCLK
CLKDIV1
CLKDIV0
PD
PDA
PDB
PDC
PDD
Configuration Register (08h)
EXTCLK<15>: External clock select.
1 = logic-level clock supplied on OSCIN.
0 = crystal or resonator connected between OSCIN
and OSCOUT (default).
CLKDIV1:CLKDIV0<14:13>: Clock divider ratio (EX
clock : ADC sample clock).
00 = 1:2 clock divider.
01 = 1:3 clock divider.
10 = 1:4 clock divider.
11 = 1:6 clock divider (default).
PD<12>: Power-down analog circuitry (reference and
SPI interface remains active).
1 = low-power mode.
0 = normal operation (default).
PD_<11:8>: ADC power-down for each channel (A, B,
C, and D).
1 = powers down analog signal path.
0 = normal operation (default).
PDDAC< 7>: DAC power-down.
1 = fine DAC buffer powered down.
0 = normal operation (default).
PDOSC<6>: Oscillator power-down.
1 = oscillator powered down (disconnects EX clock in
EX clock mode).
0 = normal operation (default).
24BIT<5>: ADC output data format.
1 = ADC data output as 24 bits.
0 = ADC data output as 16 bits (default).
Use the 24-bit ADC output in conjunction with external
digital filtering to improve signal-to-noise ratio.
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
PDDAC
PDOSC
24BIT
SCHANA
SCHANB
SCHANC
SCHAND
DECSEL
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相關代理商/技術參數(shù)
參數(shù)描述
MAX11044 制造商:MAXIM 制造商全稱:Maxim Integrated Products 功能描述:4-/6-/8-Channel, 16-Bit, Simultaneous-Sampling ADCs
MAX11044_10 制造商:MAXIM 制造商全稱:Maxim Integrated Products 功能描述:4-/6-/8-Channel, 16-Bit, Simultaneous-Sampling ADCs
MAX11044_11 制造商:MAXIM 制造商全稱:Maxim Integrated Products 功能描述:4-/6-/8-Channel, 16-/14-Bit, Simultaneous-Sampling ADCs
MAX11044_12 制造商:MAXIM 制造商全稱:Maxim Integrated Products 功能描述:4-/6-/8-Channel, 16-/14-Bit, Simultaneous-Sampling ADCs
MAX11044BECB+ 功能描述:模數(shù)轉換器 - ADC MAX11044BECB+ RoHS:否 制造商:Maxim Integrated 通道數(shù)量: 結構: 轉換速率: 分辨率: 輸入類型: 信噪比: 接口類型: 工作電源電壓: 最大工作溫度: 安裝風格: 封裝 / 箱體:
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