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參數(shù)資料
| 型號： | M68LC302CPU16VCT |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP100 |
| 封裝： | 14 X 14 MM, 1.40 MM HEIGHT, 0.50 MM PITCH, PLASITC, LQFP-100 |
| 文件頁數(shù)： | 80/128頁 |
| 文件大?。?/td> | 641K |
| 代理商： | M68LC302CPU16VCT |
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ETHERNET Controller
4-16
MC68EN302 REFERENCE MANUAL
MOTOROLA
4.2.2 ETHERNET TRANSMIT BUFFER DESCRIPTOR
Transmit data is presented to the Ethernet controller through buffers referenced by transmit
Buffer Descriptors. The Ethernet controller confirms transmission operation through the R
bit, and indicates error conditions through the other status bits in the most signficant word
of the BD. The host software must initialize the R, W, I, L, TC, and (optionally) TO bits in the
first word, the length in the second word, and the buffer pointer in the third and fourth words.
.
Figure 4-3. Ethernet Transmit Buffer Descriptor (Tx BD)
The Tx BD fields are detailed below. The unused bits (15-8) in Offset + 4 are not used by
the hardware. These unused bits are R/W by software and are ignored by hardware.
R—Ready, written by Ethernet controller and user.
0 = The data buffer associated with this BD is not ready for transmission, leaving the
software free to manipulate this BD or its associated data buffer. The Ethernet
controller clears this bit after the buffer has been transmitted or after an error
condition is encountered.
1 = The data buffer, which has been prepared for transmission by the user, has not
been transmitted or is currently being transmitted. No fields of this BD may be
written after this bit is set.
TO—Transmit Buffer Software Ownership, written by user.
This bit is provided as a software ownership bit, if needed. Hardware does not alter the value
of this bit.
L— Last (Last BD for this frame)
0 = This is not the last BD for this frame and the Ethernet controller sets R= 0 when the
buffer has been DMA’d into the MC68EN302. Status bits are not modified.
1 = The Ethernet controller sets R = 0 and modifies the DEF, HB, LC, RL, RC, UN and
CSL status bits once the buffer has been DMA’d into the MC68EN302 and frame
transmission has completed
Offset + 0
Offset + 2
Offset + 4
Offset + 6
Tx Data Buffer Pointer - A15–A0
Data Length
CSL
UN
RL
LC
TC
L
I
W
TO
R
HB
DEF
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
RC
A23–A16
Unused
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