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參數(shù)資料
| 型號(hào)： | M68LC302CPU16VCT |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP100 |
| 封裝： | 14 X 14 MM, 1.40 MM HEIGHT, 0.50 MM PITCH, PLASITC, LQFP-100 |
| 文件頁數(shù)： | 55/128頁 |
| 文件大?。?/td> | 641K |
| 代理商： | M68LC302CPU16VCT |
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MOTOROLA
MC68EN302 REFERENCE MANUAL
3-1
SECTION 3
MC68EN302 DRAM CONTROL MODULE
3.1 INTRODUCTION
The MC68EN302, like its predecessor the MC68302, can be connected with DRAM-type
memories easily. The difference in the MC68EN302 lies in the DRAM Control Module
(DCM), which was developed to provide seamless integration of the 68000 core with DRAM
memories. The MC68EN302 DRAM controller is able to support up to two 16-bit wide banks
and an address range from 128kbytes to 8Mbytes. Selection between the two banks occurs
externally through the MC68EN302 RAS1–RAS0 signals, and byte selection occurs via the
CAS1–CAS0 signals. The user is able to select cycle lengths ranging in duration from 4 to
7 clocks. The MC68EN302 also provides programmable refresh rates which can range
anywhere from 16 to 4096 system clocks, or be disabled altogether.
3.2 MEMORY MAP
Table 3-1 shows the basic memory map of the DRAM Control Module registers.
3.3 DRAM CONFIGURATION REGISTER (DCR)
This register controls the specific operation of each bank of DRAM and is initialized to zero
at hardware reset.
Bits 15–12—Reserved. Should be written to zero by the host processor. These bits are
always read as zero.
E1-E0—Refresh Enable Bits.
0 = Disable refresh operation in the corresponding DRAM bank
1 = Enable refresh operation in the corresponding bank.
Table 3-1. DRAM Controller Registers
ADDRESS
NAME
MNEMONIC
TYPE
FC
MOBA + 010
DRAM Configuration Register
DCR
Read/Write
S
MOBA + 012
DRAM Refresh Register
DRFRSH
Read/Write
S
MOBA + 014
DRAM Bank 0 Base Address Register
DBA0
Read/Write
S
MOBA + 016
DRAM Bank 1 Base Address Register
DBA1
Read/Write
S
15
14
13
12
11
10
9876543210
0000
E1
E0
PE1
PE0
P1
P0
W1
W0
WP1
WP0
S/U1
S/U0
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