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參數(shù)資料
| 型號： | M68LC302CPU16VCT |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP100 |
| 封裝： | 14 X 14 MM, 1.40 MM HEIGHT, 0.50 MM PITCH, PLASITC, LQFP-100 |
| 文件頁數(shù)： | 68/128頁 |
| 文件大?。?/td> | 641K |
| 代理商： | M68LC302CPU16VCT |
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ETHERNET Controller
MOTOROLA
MC68EN302 REFERENCE MANUAL
4-5
of space to be available in the transmit FIFO prior to beginning a DMA burst into the
MC68EN302 transmit FIFO. WMRK is typically set to 16.
WMRK1–WMRK0, when used in conjunction with BLIM2–BLIM0, allows the system
designer to configure the MC68EN302 device for expected bus latency.
BLIM2–BLIM0—Burst Limit. (R/W)
BLIM2–BLIM0 controls the maximum length of a DMA burst in accesses from the bus
interface unit. BLIM is typically set to 8 for 16 bit systems.
000 = 1 Access
001 = 2 Accesses
010 = 4 Accesses
011 = 8 Accesses
100 = 16 Accesses
101 = 32 Accesses
110 = 64 Accesses
111 = Unlimited
4.1.3 ETHERNET MAXIMUM RECEIVE BUFFER LENGTH (EMRBLR)
The EMRBLR register determines the maximum size of all receive buffers. Because the
maximum frame is limited to 1518, only bits 10–0 are written by the user. The value written
into the maximum receive buffer length register must account for the receive CRC which is
always written into the last receive buffer. To allow one maximum size frame per buffer,
EMRBLR must be set to 0000010111101110 or larger. The EMRBLR must be evenly
divisible by 2. To ensure this, bit 0 is forced low. Only non-zero values are considered to be
valid, therefore this register should be written after reset, but before Ethernet operation is
enabled. All implemented bits are R/W. This register is cleared upon a hardware reset.
5–11—Reserved.
Should be written to zero by the host processor. These bits are always read as zero.
MRBL—Maximum receive buffer length.
Must be programmed to a non-zero value for operation.
0—Reserved.
Must be written as zero by the host processor. This bit is always read as zero.
15
14
13
12
11
10
9876543210
00000
MAXIMUM RECEIVE BUFFER LENGTH
0
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