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參數(shù)資料
| 型號： | M68LC302CPU16VCT |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP100 |
| 封裝： | 14 X 14 MM, 1.40 MM HEIGHT, 0.50 MM PITCH, PLASITC, LQFP-100 |
| 文件頁數(shù)： | 72/128頁 |
| 文件大?。?/td> | 641K |
| 代理商： | M68LC302CPU16VCT |
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ETHERNET Controller
MOTOROLA
MC68EN302 REFERENCE MANUAL
4-9
BSYEN—Busy Interrupt Enable.
Enable interrupts when BSY is set.
TBIEN—Transmit Buffer Interrupt Enable.
Enable interrupts when TBINT is set.
RBIEN—Receive Buffer Interrupt Enable.
Enable interrupts when RBINT is set.
4.1.7 ETHERNET CONFIGURATION (ECNFIG)
The Ethernet Configuration register provides protocol configuration information to the
Ethernet controller and can be written only when the ETHER_EN bit in the ECNTRL register
is clear. This register is cleared on a hardware reset.
15–4—Reserved.
Should be written to zero by the host processor. These bits are always read as zero.
RDT—Receive Disable on Transmit
0 = Receive path operates independently of transmit.
The purpose of this bit is to block reception of frames while this node is transmitting. If FDEN
= 1, this bit must be 0.
If FDEN = 0, this bit should be 1, except when:
1. LOOP = 1 to select internal feedback.
2. An external loopback is being performed.
3. This node wants to receive its own transmit frames for monitoring purposes.
HBC—HeartBeat Control.
0 = The heartbeat check is not performed. Following end of transmission, the HB bit in
the TxBD will be cleared.
1 = The heartbeat check is performed. Following end of transmission, if CLSN is not
asserted during the heartbeat window, the HB bit in the TxBD will be set.
FDEN—Full Duplex Enable.
0 = Carrier Sense and Collision inputs are active, deference and collision handling is
according to IEEE 802.3
1 = Frames are transmitted independent of Carrier Sense and Collision inputs.
15
14
13
12
11
10
987654
3
210
000000000000
RDT
HBC FDEN LOOP
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