參數(shù)資料
型號(hào)： M68LC302CPU16VCT
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 4 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP100
封裝： 14 X 14 MM, 1.40 MM HEIGHT, 0.50 MM PITCH, PLASITC, LQFP-100
文件頁數(shù)： 66/128頁
文件大?。?/td> 641K
代理商： M68LC302CPU16VCT
ETHERNET Controller
MOTOROLA
MC68EN302 REFERENCE MANUAL
4-3
Bits in the registers are R/W unless noted otherwise. Unimplemented bits will return 0 on
reads. If reserved memory locations are accessed, DTACK is not returned.
4.1.1 ETHERNET CONTROL REGISTER (ECNTRL)
The ECNTRL register controls MC68EN302 Ethernet controller operation. All implemented
bits in this register are R/W. This register is $0000 following system reset.
15–3 Reserved. Should be written to zero by the host processor. These bits are always
read as zero.
GTS—Graceful Transmit Stop.
0 = No change in Ethernet controller operation
1 = The Ethernet controller will stop transmission after all frames that are currently
being transmitted have completed. See GRA in 4.1.5 Interrupt Event Register
(INTR_EVENT).
ETHER_EN—Ethernet Enable.
0 = Reception is immediately stopped and transmission ends following the appending
of a bad CRC to any frame currently being transmitted. Buffer descriptor(s)
corresponding to an aborted transmit frame are not updated following ETHER_EN
deassertion. In this situation, the DMA, buffer descriptor and FIFO control logic is
reset along with the buffer descriptor and FIFO pointers.
1 = The Ethernet controller is enabled and reception and transmission of frames may
occur.
RESET—Ethernet Controller Reset.
0 = A reset is performed locally within the Ethernet controller. ETHER_EN is cleared
and all other Ethernet controller registers take their reset values. During Ethernet
controller reset, the Buffer Descriptor Table and the CAM Entry Table can not be
read or written. Any transmission/reception currently in progress is abruptly
aborted.
1 = The MC68EN302 Ethernet controller operates normally
4.1.2 ETHERNET DMA CONFIGURATION STATUS REGISTER (EDMA)
The EDMA register allows user control of the DMA unit and may be written only when the
ETHER_EN bit in the ECNTRL register is cleared. This register is cleared by a hardware
reset.
BDERR 6–0—Buffer descriptor error number.
15
14
13
12
11
10
98765432
1
0
0000000000000
GTS
ETHER_EN
RESET
15
14
13
12
11
10
9
8
7
6
5
43210
BDERR<6:0>
0
BDSIZE<1:0>
TSRLY
WMRK<1:0>
BLIM<2:0>
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