參數(shù)資料
型號(hào): M36DR232
廠商: 意法半導(dǎo)體
英文描述: 32 Mbit 2Mb x16, Dual Bank, Page Flash Memory and 2 Mbit 128K x16 SRAM, Multiple Memory Product
中文描述: 32兆位的2Mb x16插槽,雙行,頁(yè)閃存和2兆位128K的x16的SRAM,多個(gè)存儲(chǔ)產(chǎn)品
文件頁(yè)數(shù): 25/46頁(yè)
文件大小: 329K
代理商: M36DR232
25/46
M36D232A, M36DR232B
Note: 1.
I
DDES
and
I
DDWS
are specified with device deselected. If device is read while in erase suspend, current draw is sum of
I
DDES
and
DDR.
If the device is read while in program suspend, current draw is the sum of
I
DDWS
and
I
DDR
.
Table 25. Flash Read AC Characteristics
(TA = –40 to 85°C; V
DDF
= 1.65V to 2.2V)
Note: 1. Sampled only, not 100% tested.
2. GF may be delayed by up to t
ELQV
- t
GLQV
after the falling edge of EF without increasing t
ELQV
V
PPL
Program Voltage
(Program or
Erase operations)
Program Voltage
(Program or
Erase operations)
Program Voltage
(Program and
Erase lock-out)
Flash
1.65
2.2
V
V
PPH
Flash
11.4
12.6
V
V
PPLK
Flash
1
V
Symbol
Alt
Parameter
Test Condition
Flash
Unit
100
120
Min
Max
Min
Max
t
AVAV
t
RC
Address Valid to Next Address
Valid
EF = V
IL
, GF = V
IL
100
120
ns
t
AVQV
t
ACC
Address Valid to Output Valid
(Random)
EF = V
IL
, GF = V
IL
100
120
ns
t
AVQV1
t
PAGE
Address Valid to Output Valid
(Page)
EF = V
IL
, GF = V
IL
35
45
ns
t
AXQX
t
OH
Address Transition to Output
Transition
EF = V
IL
, GF = V
IL
0
0
ns
t
EHQX
t
OH
Chip Enable High to Output
Transition
GF = V
IL
0
0
ns
t
EHQZ(1)
t
HZ
Chip Enable High to Output Hi-Z
GF = V
IL
25
35
ns
t
ELQV(2)
t
CE
Chip Enable Low to Output Valid
GF = V
IL
100
120
ns
t
ELQX(1)
t
LZ
Chip Enable Low to Output
Transition
GF = V
IL
0
0
ns
t
GHQX
t
OH
Output Enable High to Output
Transition
EF = V
IL
0
0
ns
t
GHQZ(1)
t
DF
Output Enable High to Output
Hi-Z
EF = V
IL
25
35
ns
t
GLQV(2)
t
OE
Output Enable Low to Output
Valid
EF = V
IL
25
35
ns
t
GLQX(1)
t
OLZ
Output Enable Low to Output
Transition
EF = V
IL
0
0
ns
Symbol
Parameter
Device
Test Condition
Min
Typ
Max
Unit
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