
REVISION HISTORY
Rev.
Date
Description
Page
Summary
C-22
M32C/85 Group(M32C/85, M32C/85T) Hardware Manual
Intelligent I/O
272
Figure 22.1 Intelligent I/O Block Diagram BE1OUT added
273
Figure 22.2 Intelligent I/O Communication Block Diagram Diagram modified
287
Figure 22.13 Timer Measurement Function (1) The second condition modified
290
Table 22.8 Waveform Generating Function Associated Register Settings
Note modified
299
Figure 22.20 G0RB and G1RB Registers Value after reset modified
300
Figure 22.22 G0MR and G1MR Registers UFORM bit name changed
301
Figure 22.23 G0EMR and G1EMR Registers Bit 0 modifed to RW
302
Figure 22.24 G1ETC Register Bits 2 to 0 function changed
305
Figure 22.27 G1IRF Register Note 2 modified
310
Table 22.19 Pin Settings (4) P152 setting with the PS9 register changed
CAN Module
318
Table 23.1 CAN Module Specifications Time Stamp Function specification
modified
320
Figure 23.2 Message Slot Buffer and Message Slot Diagram modified
321
Table 23.2 Pin Settings P83 setting with the IPS register changed
322
Figure 23.3 C0CTLR0 and C1CTLR0 Registers Note 3 added
323
23.1.1.3 BASICCAN Bit Procedure (5) modified
324
23.1.1.6 ECRESET Bit The CAN0OUT pin on Note 2 modified to the CANiOUT pin
332
23.1.6.5 SJW1 and SJW0 Bits Description modified
333
Figure 23.9 C0BRP and C1BRP Registers Value after reset modified
342
23.1.16.1 CMOD Bit Note 1 modified
351
Subsection description modified
361
Subsection description modified
365
Figure 23.39 Example of CAN Data Frame Receive Operation Diagram
modified
366
Figure 23.40 Operation Timing when CAN Bus Error Occurs Diagram modified
368
23.4.2.2 When the INTSEL Bit is Set to "1" Description modified
Programmable I/O Ports
370
24.3 Function Select Register Aj (PSJ Register) (i=0 to 5, 8, 9) changed to (i=0
to 3, 5, 8, 9)
373
Figure 24.2 Programmable I/O Ports (2) Diagram modified
376
Figure 24.6 P0 to P15 Registers Note 4 modified
385
Figure 24.15 PUR2 Register Note 3 deleted
387
Figure 24.17 IPS Register Note 2 modified
Flash Memory Version
399
Figure 25.4 FMR0 Register Note 5 modified
401
25.3.3.4 FMSTP Bit Description modified