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22. Intelligent I/O (Communication Function)
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8
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3
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Figure 22.30 Transmit and Receive Operation
n+2
m
Base Timer
The base timer is reset by the channel 0
waveform generating function
ISRxD1 pin Input
(received data)
ISTxD1 pin Output
(data to be transmitted)
ISCLK1 pin Output
(transmit clock in the
channel 3 generating
function)
SIO1TR bit
when IRS=0
(no data in the
G1TB register)
Write to the G1TB register
ISRxDi pin Input
(received data)
ISTxDi pin Output
(data to be transmitted)
SIOiTR bit
when IRS=0
(no data in the
GiTB register)
SIOiTR bit
when IRS=1
(transmission completed)
Write to the GiTB register
The above applies to the following conditions:
The CKDIR bit in the G1MR register is set to "0" (internal clock)
The CCS3 and CCS2 bits in the CCS register are set to "002"
The UFORM bit in the G1MR register is set to "0" (LSB first)
The IPOL and OPOL bits in the G1CR register are set to "0" (no inverse)
n : Setting value of the G1PO0 register
m : Setting value of the G1PO3 register
SIO1TR bit : Bit in the IIO3IR register
SIO1RR bit : B it in the IIO2IR register
IRS bit
: Bit in the G1MR register
The above applies to the following conditions:
The CKDIR bit in the GiMR register is set to "0" (internal clock)
The CCS1 and CCS0 bits or the CCS3 and CCS2 bits in the CCS register
are set to "102" or "112"
The UFORM bit in the GiMR register is set to "0" (LSB first)
The IPOL and OPOL bits in the GiCR register are set to "0" (no inverse)
SIOiTR bit : Bit in the IIOjIR register (j=1, 3)
SIOiRR bit : B it in the IIOkIR register (k=0, 2)
IRS bit
: Bit in the GiMR register
TE bit
: Bit in the GiCR register
i=0, 1
"1"
Bit 1
Bit 2
Bit 6
Bit 0
Bit 7
Bit 1
Bit 2
Bit 6
Bit 0
Bit7
SIO1RR bit
SIOiRR bit
Write "0" by program
if setting to "0"
Write "0" by program if setting to "0"
Transfer clock
f8, f2n or
external clock
TE bit
Bit 1
Bit 2
Bit 6
Bit 0
Bit7
Bit 1
Bit 2
Bit 6
Bit 0
Bit7
Write "0" by program
if setting to "0"
Write "0" by program
if setting to "0"
Write "0" by program if setting to "0"
(1) When the Commumictin Clock is Set to f8, f2n or External Clock
(Communication Units 0 and 1)
(2) When the Communication Clock is Generated in Channel 3 Phase-Delayed Waveform Output Mode
(Communication Unit 1)
"0"
"1"
"0"
"1"
"0"
"1"
"0"
"1"
"0"
"1"
"0"