![](http://datasheet.mmic.net.cn/30000/M30855FHTGP_datasheet_2359399/M30855FHTGP_533.png)
REVISION HISTORY
Rev.
Date
Description
Page
Summary
C-16
M32C/85 Group(M32C/85, M32C/85T) Hardware Manual
291
Table 22.9 Single-Phase Waveform Output Mode Specifications Setting
value of the G1PO0 register changed
292
Figure 22.16 Single-Phase Waveform Output Mode Setting value of registers
added; condition added
293
Table 22.10 Phase-Delayed Waveform Output Mode Specifications Setting
value of the G1PO0 register changed
294
Figure 22.17 Phase-Delayed Waveform Output Mode Setting value of regis-
ters added; condition added
295
Table 22.11 SR Waveform Output Mode Specifications Setting value of the
G1PO0 register changed
297
Figure 22.18 SR Waveform Output Mode Setting value of registers added;
condition added
299
Figure 22.20 G0CR to G1CR Registers, G0RB to G1RB Registers B14 in the
G0RB to G1RBregisters changed to PER bit
309
Table 22.14 Clock Settings (Group 1) Setting value of the G1PO0 register
changed
310
Table 22.16 Pin Settings (1) Registers set for P76 and P77 deleted
Table 22.16 Pin Settings (4) Registers set for P150 and P151 deleted
312
Table 22.20 UART Mode Specifications ISTxD1 and ISRxD1 Polarity Inverse
function deleted
313
Table 22.21 Clock Settings Input from ISCLK1 deleted; note 4 deleted
Table 22.22 Registers to be Used and Settings UFORM bit function modified;
CSS3 to CSS2 bit functions modified
314
Figure 22.31 Transmit Operation Figure modified
Figure 22.32 Receive Operation Figure modified
315
22.4.3 HDLC Data Processing Mode Description modified
Table 22.25 HDLC Processing Mode Specifications Transmit Start Condition
and Receive Start Condition brought together to Data Processing Start Condition
317
Table 22.28 Registers to be Used and Settings G1PO1 register function
modified
Programmable I/O Ports
368
Figure 24.1 Programmable I/O Ports (1) P150 and P151 deleted; P152 and
P157 added
370
Figure 24.3 Programmable I/O Ports (3) P15 deleted; P150 added
371
Figure 24.5 PD0 to PD15 Register Note 2 modified
372
Figure 24.6 P0 to P15 Register Note 1 modified
381
Figure 24.15 PUR0 Register, PUR1 Register and PUR2 Register Note 1 each
added to the PUR0 Register and PUR1 Register
383
Figure 24.17 PCR Register and IPS Register Note 1 added to the PCR register