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25. Flash Memory Version
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25.3.5 Software Commands
Read or write 16-bit commands and data from or to even addresses in the user ROM area, in 16-bit units.
When writing a command code, 8 high-order bits (D15 to D8) are ignored.
Table 25.4 Software Commands
Command
Program
Clear Status Register
Read Array
Read Status Register
First Bus Cycle
Second Bus Cycle
Lock Bit Program
Erase All Unlocked Block(1)
Block Erase
Read Lock Bit Status
Write
Mode
Read
Write
Mode
X
BA
X
WA
BA
Address
SRD
xxD016
WD
xxD016
Data
(D15 to D0)
xxFF16
xx7016
xx5016
xx4016
xx7716
xxA716
xx2016
xx7116
Data
(D15 to D0)
X
WA
BA
X
Address
NOTES:
1. Blocks 0 to 12 can be erased by the erase all unlocked block command.
Block A cannot be erased. The block erase command must be used to erase the block A.
SRD:
Data in the SRD register (D7 to D0)
WA:
Address to be written (The address specified in the the first bus cycle is the same even address
as the address specified in the second bus cycle.)
WD:
16-bit write data
BA:
Highest-order block address (must be an even address)
X:
Any even address in the user ROM space
xx:
8 high-order bits of command code (ignored)
25.3.5.1 Read Array Command
The read array command reads the flash memory.
Read array mode is entered by writing command code "xxFF16" in the first bus cycle. Content of a
specified address can be read in 16-bit units after the next bus cycle.
The microcomputer remains in read array mode until another command is written. Therefore, contents
from multiple addresses can be read consecutively.
25.3.5.2 Read Status Register Command
The read status register command reads the SRD register (refer to 25.3.7 Status Register for detail).
By writing command code "xx7016" in the first bus cycle, the SRD register can be read in the second
bus cycle. Read an even address in the user ROM area.
Do not execute this command in EW mode 1.
25.3.5.3 Clear Status Register Command
The clear status register command clears the SRD register. By writing "xx5016" in the first bus cycle,
the FMR07 and FMR06 bits in the FMR0 register are set to "002" and the SR5 and SR4 bits in the SRD
register are set to "002".