
Page 114
4
9
4
f
o
5
0
2
,
1
0
.
l
u
J
3
0
.
1
.
v
e
R
3
0
1
0
-
7
3
0
B
9
0
J
E
R
11. Interrupts
)
T
5
8
/
C
2
3
M
,
5
8
/
C
2
3
M
(
p
u
o
r
G
5
8
/
C
2
3
M
Figure 11.4 Interrupt Control Register (2)
11.6.2.1 ILVL2 to ILVL0 Bits
The ILVL2 to ILVL0 bits determines an interrupt priority level. The higher the interrupt priority level is,
the higher interrupt priority is.
When an interrupt request is generated, its interrupt priority level is compared to IPL. This interrupt is
acknowledged only when its interrupt priority level is higher than IPL. When the ILVL2 to ILVL0 bits
are set to "0002" (level 0), its interrupt is ignored.
11.6.2.2 IR Bit
The IR bit is automatically set to "1" (interrupt requested) when an interrupt request is generated. The
IR bit is automatically set to "0" (no interrupt requested) after an interrupt request is acknowledged and
an interrupt routine in the corresponding interrupt vector is executed.
The IR bit can be set to "0" by program. Do not set to "1".
Interrupt Control Register
After Reset
XX00 X0002
Address
009E16, 007E16, 009C16
007C16, 009A16, 007A16
Symbol
INT0IC to INT2IC
INT3IC to INT5IC(1)
RW
ILVL0
ILVL1
ILVL2
Interrupt Priority Level
Select Bit
IR
POL
LVS
(b7 - b6)
Interrupt Request Bit
Polarity Switch Bit
Level Sensitive/Edge
Sensitive Switch Bit
0 : Requests no interrupt
1 : Requests an interrupt(2)
0 : Selects falling edge or "L"(3)
1 : Selects rising edge or "H"
0 : Edge sensitive
1 : Level sensitive(4)
Nothing is assigned. When write, set to "0".
When read, its content is indeterminate.
0 0 0 : Level 0 (interrupt disabled)
0 0 1 : Level 1
0 1 0 : Level 2
0 1 1 : Level 3
1 0 0 : Level 4
1 0 1 : Level 5
1 1 0 : Level 6
1 1 1 : Level 7
b2 b1 b0
Bit Name
Function
Bit
Symbol
NOTES:
1. When a 16-bit data bus is used in microprocessor or memory expansion mode, each INT3 to INT5
pin is used as the data bus. Set the ILVL2 to ILVL0 bits in the INT3IC, INT4IC and INT5IC registers
to "0002".
2. The IR bit can be set to "0" only (do not set to "1").
3. Set the POL bit to "0" when a corresponding bit in the IFSR register is set to "1" (both edges).
4. When setting the LVS bit to "1" , set a corresponding bit in the IFSR register to "0" (one edge).
b7
b6
b5
b4
b3
b2
b1
b0