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22. Intelligent I/O
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Figures 22.3 to 22.8 show registers associated with the intelligent I/O base timer, the time measurement
function and waveform generating function. (For registers associated with the communication function, see
Figures 22.19 to 22.28.)
Figure 22.3 G1BT Register and G1BCR0 Register
Base Timer Register 1(2)
Symbol
Address
After Reset
G1BT
012116 - 012016
Indeterminate
RW
Function
b0
Setting Range
000016 to FFFF16
b8
b15
b7
When the base timer is counting:
When read, the value of the base timer can be
read.
When write, the counter starts counting from the
value written. When the base timer is reset, the
G1BT register is set to "000016"(1).
When the base timer is reset:
The G1BT register is set to "000016" but value is
indeterminate. No value is written(1).
NOTES:
1. The base timer stops only when the BCK1 and BCK0 bits in the G1BCR0 register are set to "002" (clock
stopped). The base timer counts when the BCK1 and BCK0 bits are set to a value other than "002".
When the BTS bit in the G1BCR1 register is set to "0", the base timer is reset continually, remaining set
to "000016". This, in effect, places the base timer in a "no counting" state. When the BTS bit is set to "1",
this state is cleared and counting starts.
2. The G1BT register reflects the value of the base timer, with a delay of one half fBT1 cycle.
Base Timer Control Register 10
Symbol
Address
After Reset
G1BCR0
012216
0016
RW
Bit Name
Function
Bit
Symbol
: Clock stops
: Do not set to this value
: Two-phase pulse signal is applied(1)
: f1
b1
0
1
b0
0
1
0
1
BCK0
BCK1
DIV0
Count Source
Select Bit
DIV1
Count Source
Divide Ratio
Select Bit
DIV2
DIV3
IT
Base Timer
Interrupt Select Bit
0 : Bit 15 overflows
1 : Bit 14 overflows
DIV4
If setting value is n (n = 0 to 31),
count source is divided by 2(n + 1).
No division if n=31.
(n=0) 0 0 0 0 0 : Divide-by-2
(n=1) 0 0 0 0 1 : Divide-by-4
(n=2) 0 0 0 1 0 : Divide-by-6
(n=30) 1 1 1 1 0 : Divide-by-62
(n=31) 1 1 1 1 1 : No division
b6 b5 b4 b3 b2
NOTES:
1. This setting can be used only when the UD1 and UD0 bits in the G1BCR1 register are set to "102"
(two-phase signal processing mode). Do not set the BCK1 and BCK0 bits to "102" in other modes.
b7
b6
b5
b4
b3
b2
b1
b0