參數(shù)資料
型號(hào)： M306H3MC-XXXFP
元件分類： 微控制器/微處理器
英文描述： 16-BIT, MROM, 10 MHz, MICROCONTROLLER, PQFP116
封裝： 20 X 20 MM, 0.65 MM PITCH, PLASTIC, LQFP-116
文件頁數(shù)： 65/135頁
文件大?。?/td> 2583K
代理商： M306H3MC-XXXFP
Rev.1.00
2004.03.23
page 35 of 320
M306H3MC-XXXFP/FCFP
(10) Software Wait
Software wait states can be inserted by using the PM17 bit in the PM1 register, the CS0W to CS3W bits
in the CSR register, and the CSE register. The SFR area is unaffected by these control bits. This area is
always accessed in 2 BCLK.
________
To use the RDY signal, set the corresponding CS3W to CS0W bit to “0”(with wait state). Figure 2.4.11
shows the CSE register. Table 2.4.10 shows the software wait related bits and bus cycles. Figure 2.4.12
and 2.4.13 show the typical bus timings using software wait.
(9) External Bus Status When Internal Area Accessed
Table 2.4.9 shows the external bus status when the internal area is accessed.
Table 2.4.9. External Bus Status When Internal Area Accessed
Item
SFR accessed
Internal ROM, RAM accessed
A0 to A19
Address output
Maintain status before accessed
address of external area or SFR
D0 to D15
When read
High-impedance
When write
Output data
Undefined
RD, WR, WRL, WRH
RD, WR, WRL, WRH output
Output “H”
BHE
BHE output
Maintain status before accessed
status of external area or SFR
CS0 to CS3
Output “H”
ALE
Output “L”
Figure 2.4.11. CSE Register
Function
Bit symbol
Bit name
Chip select expansion control register
Symbol
Address
After reset
CSE
001B16
0016
RW
b7
b6
b5
b4
b3
b2
b1
b0
CSE00W
CS0 wait expansion bit
0 0: 1 wait
0 1: 2 waits
1 0: 3 waits
1 1: Must not be set
b1 b0
CSE01W
(Note)
CSE10W
CS1 wait expansion bit
0 0: 1 wait
0 1: 2 waits
1 0: 3 waits
1 1: Must not be set
b3 b2
CSE11W
(Note)
CSE20W
CS2 wait expansion bit
0 0: 1 wait
0 1: 2 waits
1 0: 3 waits
1 1: Must not be set
b5 b4
CSE21W
(Note)
CSE30W
CS3 wait expansion bit
0 0: 1 wait
0 1: 2 waits
1 0: 3 waits
1 1: Must not be set
b7 b6
CSE31W
(Note)
Note: Set the CSiW bit (i = 0 to 3) in the CSR register to “0” (with wait state) before writing to the CSEi1W to
CSEi0W bits. If the CSiW bit needs to be set to “1” (without wait state), set the CSEi1W to CSEi0W bits to “
002” before setting it.
RW
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