參數(shù)資料
型號: M306H3MC-XXXFP
元件分類: 微控制器/微處理器
英文描述: 16-BIT, MROM, 10 MHz, MICROCONTROLLER, PQFP116
封裝: 20 X 20 MM, 0.65 MM PITCH, PLASTIC, LQFP-116
文件頁數(shù): 107/135頁
文件大?。?/td> 2583K
代理商: M306H3MC-XXXFP
Rev.1.00
2004.03.23
page 73 of 320
M306H3MC-XXXFP/FCFP
2.7.10 Address Match Interrupt
An address match interrupt request is generated immediately before executing the instruction at the ad-
dress indicated by the RMADi register (i=0 to 3). Set the start address of any instruction in the RMADi
register. Use the AIER register’s AIER0 and AIER1 bits and the AIER2 register’s AIER20 and AIER21 bits
to enable or disable the interrupt. Note that the address match interrupt is unaffected by the I flag and IPL.
For address match interrupts, the value of the PC that is saved to the stack area varies depending on the
instruction being executed (refer to “Saving Registers”).
(The value of the PC that is saved to the stack area is not the correct return address.) Therefore, follow one
of the methods described below to return from the address match interrupt.
Rewrite the content of the stack and then use the REIT instruction to return.
Restore the stack to its previous state before the interrupt request was accepted by using the POP or
similar other instruction and then use a jump instruction to return.
Table 2.7.6 shows the value of the PC that is saved to the stack area when an address match interrupt
request is accepted.
Note that when using the external bus in 8 bits width, no address match interrupts can be used for external
areas.
Figure 2.7.13 shows the AIER, AIER2, and RMAD0 to RMAD3 registers.
Table 2.7.6. Instruction Just Before Execution and Address Stored in Stack When There Occurs
Interrupts
Table 2.7.7. Relationship Between Address Match Interrupt Sources and Associated Registers
Address match interrupt sources Address match interrupt enable bit
Address match interrupt register
Address match interrupt 0
AIER0
RMAD0
Address match interrupt 1
AIER1
RMAD1
Address match interrupt 2
AIER20
RMAD2
Address match interrupt 3
AIER21
RMAD3
16-bit op-code instruction
Instruction shown below among 8-bit operation code instructions
ADD.B:S
#IMM8,dest
SUB.B:S
#IMM8,dest
AND.B:S
#IMM8,dest
OR.B:S
#IMM8,dest
MOV.B:S
#IMM8,dest
STZ.B:S
#IMM8,dest
STNZ.B:S
#IMM8,dest
STZX.B:S
#IMM81,#IMM82,dest
CMP.B:S
#IMM8,dest
PUSHM
src
POPM dest
JMPS
#IMM8
JSRS
#IMM8
MOV.B:S
#IMM,dest (However, dest=A0 or A1)
Instructions other than the above
Instruction at the address indicated by the RMADi register
Value of the PC that is
saved to the stack area
The address
indicated by the
RMADi register +2
The address
indicated by the
RMADi register +1
Value of the PC that is saved to the stack area : Refer to “Saving Registers”.
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