參數(shù)資料
型號(hào): M306H3MC-XXXFP
元件分類: 微控制器/微處理器
英文描述: 16-BIT, MROM, 10 MHz, MICROCONTROLLER, PQFP116
封裝: 20 X 20 MM, 0.65 MM PITCH, PLASTIC, LQFP-116
文件頁(yè)數(shù): 62/135頁(yè)
文件大?。?/td> 2583K
代理商: M306H3MC-XXXFP
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Rev.1.00
2004.03.23
page 32 of 320
M306H3MC-XXXFP/FCFP
________
Figure 2.4.9. Example in which Wait State was Inserted into Read Cycle by RDY Signal
BCLK
RD
CSi
(i=0 to 3)
RDY
tsu(RDY - BCLK)
BCLK
RD
CSi
(i=0 to 3)
RDY
tsu(RDY - BCLK)
In an instance of separate bus
In an instance of multiplexed bus
Accept timing of RDY signal
: Wait using RDY signal
: Wait using software
Accept timing of RDY signal
Shown above is the case where CSEiW to CSEi1W (i = 0 to 3) bits in the CSE register are “00 2” (one wait state).
________
(6) The RDY Signal
This signal is provided for accessing external devices which need to be accessed at low speed. If input on
________
the RDY pin is asserted low at the last falling edge of BCLK of the bus cycle, one wait state is inserted in
________
the bus cycle. While in a wait state, the following signals retain the state in which they were when the RDY
signal was acknowledged.
______
______ ________
________
______
________
__________
A0 to A19, D0 to D15, CS0 to CS3, RD, WRL, WRH, WR, BHE, ALE, HLDA
________
Then, when the input on the RDY pin is detected high at the falling edge of BCLK, the remaining bus cycle
is executed. Figure 2.4.9 shows example in which the wait state was inserted into the read cycle by the
________
RDY signal. To use the RDY signal, set the corresponding bit (CS3W to CS0W bits) in the CSR register
________
to “0” (with wait state). When not using the RDY signal, process the RDY pin as an unused pin.
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