參數(shù)資料
型號: M306H3MC-XXXFP
元件分類: 微控制器/微處理器
英文描述: 16-BIT, MROM, 10 MHz, MICROCONTROLLER, PQFP116
封裝: 20 X 20 MM, 0.65 MM PITCH, PLASTIC, LQFP-116
文件頁數(shù): 102/135頁
文件大?。?/td> 2583K
代理商: M306H3MC-XXXFP
Rev.1.00
2004.03.23
page 69 of 320
M306H3MC-XXXFP/FCFP
Interrupt Priority
If two or more interrupt requests are generated while executing one instruction, the interrupt request that
has the highest priority is accepted.
For maskable interrupts (peripheral functions), any desired priority level can be selected using the ILVL2 to
ILVL0 bits. However, if two or more maskable interrupts have the same priority level, their interrupt priority
is resolved by hardware, with the highest priority interrupt accepted.
The watchdog timer and other special interrupts have their priority levels set in hardware. Figure 2.7.8
shows the priorities of hardware interrupts.
Software interrupts are not affected by the interrupt priority. If an instruction is executed, control branches
invariably to the interrupt routine.
Returning from an Interrupt Routine
The FLG register and PC in the state in which they were immediately before entering the interrupt se-
quence are restored from the stack by executing the REIT instruction at the end of the interrupt routine.
Thereafter the CPU returns to the program which was being executed before accepting the interrupt re-
quest.
Return the other registers saved by a program within the interrupt routine using the POPM or similar in-
struction before executing the REIT instruction.
Interrupt Priority Resolution Circuit
The interrupt priority resolution circuit is used to select the interrupt with the highest priority among those
requested.
Figure 2.7.9 shows the circuit that judges the interrupt priority level.
Figure 2.7.8. Hardware Interrupt Priority
Reset
Watchdog timer
Peripheral function
Single step
Address match
High
Low
NMI
DBC
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