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| 型號： | M-ORSO82G52BM680-DB |
| 廠商： | LATTICE SEMICONDUCTOR CORP |
| 元件分類： | FPGA |
| 英文描述： | FPGA, 1296 CLBS, 333000 GATES, PBGA680 |
| 封裝： | PLASTIC, FBGA-680 |
| 文件頁數(shù)： | 98/123頁 |
| 文件大?。?/td> | 2207K |
| 代理商： | M-ORSO82G52BM680-DB |
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Lattice Semiconductor
ORCA ORSO82G5 Data Sheet
76
Table 19. Per-Channel Control Register Descriptions (continued)
(0x) Abso-
lute
Address
Bit
Name
Reset
Value
(0x)
Description
Mode
30804 - AA
30814 - AB
30824 - AC
30834 - AD
30904 - BA
30914 - BB
30924 - BC
30934 - BD
[0]
LCKREFN_xx
00
0 = Lock receiver to reference clock (REFCLK)
1 = Lock receiver to HDINxx data
Both
[1]
LOOPENB_xx
LOOPENB_xx =1 Enable high-speed internal
loopback from TX to RX. Disable the HDOUT
buffers.
Both
[2]
DISABLE_TX_xx
Disable Transmitter, For DISABLE_TX = 1 the
TX Link is disabled. The disabled link is ignored
by the Output Port Controller (OPC) and inter-
nally generated idle cells are transmitted on the
link.fIf the link is disabled during the transmis-
sion of a cell on the link, the entire cell is trans-
mitted before the link is declared invalid.
Cell
[3]
DISABLE_RX_xx
Disable Receiver, DISABLE_RX = 1 disables
the RX link for cell processing by the Input Port
Controller (IPC). The IPC will not read cells
from a link if this bit is set for that link
Cell
[4]
CELL_BIP_INH_xx
Cell BIP (Check) Inhibit, CELL_BIP_INH = 1
prevents cells from being dropped due to a Cell
BIP error, in the RX path. If this bit is not set,
then cells will be dropped automatically if a cell
bip error is detected by the core. The CELL-
DROP signal across the core-FPGA interface
will be active only if this bit is NOT set.
Cell
[5]
CELL_SEQ_INH_xx
Cell Sequence (Checking) Inhibit,
CELL_SEQ_INH = 1 prevents cells in the RX
path from being dropped due to a sequence
error. If this bit is not set, then cells will be
dropped automatically if a sequence error is
detected internally. The CELLDROP signal
across the core-FPGA interface will be active
only if this bit is NOT set.
Cell
[6]
AUTO_TOH_xx
Automatic TOH Generation, AUTO_TOH_xx =1
enables the TX core to automatically generate
TOH bytes. All the FORCE_* register bits are
valid only if this bit is set. This bit should be set
to 1 in Cell Mode. It can be set to 1or 0 in
SONET Mode. If this bit is not set, then user
has to provide all the TOH bytes.
SONET
[7]
FMPU_RESYNC1_xx
Single channel alignment FIFO reset. Rising
edge sensitive. Write a 0 and then a 1 to enable
this bit. When enabled, the read pointer in the
alignment FIFO is reset to the middle of the
FIFO. This bit is valid only when
FMPU_SYNMODE_xx = 00 (no multi channel
alignment)
SONET
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