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| 型號： | M-ORSO82G52BM680-DB |
| 廠商： | LATTICE SEMICONDUCTOR CORP |
| 元件分類： | FPGA |
| 英文描述： | FPGA, 1296 CLBS, 333000 GATES, PBGA680 |
| 封裝： | PLASTIC, FBGA-680 |
| 文件頁數(shù)： | 33/123頁 |
| 文件大?。?/td> | 2207K |
| 代理商： | M-ORSO82G52BM680-DB |
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Lattice Semiconductor
ORCA ORSO82G5 Data Sheet
17
ORSO82G5 Embedded Core Detailed Description
The ORSO82G5 consists of 8 channels each with a high-speed SERDES macro that performs clock data recovery,
serializing and deserializing functions. There is also additional logic for SONET mode and Cell mode data synchro-
nization formatting and scrambling/descrambling. For all modes, the data paths can be characterized as the trans-
mit path (FPGA to backplane) and receive path (backplane to FPGA); however the interface signal assignments
between the FPGA logic and the core differ depending on the operating mode selected.
The three main operating modes in the ORSO82G5 are:
SERDES only mode
SONET mode
Cell mode
–Two-link sub-mode
– Eight-link sub-mode
The SONET and Cell modes each support sub-modes that can be selected by enabling or disabling certain func-
tions through programmable register bits. Following the basic TX and RX architecture descriptions, the data format-
ting and logical implementations supporting each of the operational modes are described.
Top Level Description - Transmitter (TX) and Receiver (RX) Architectures
The next sections give a top level description of the transmitter and receive architectures. The high-speed transmit
and receive serial data can operate at 1.0—2.7 Gbits/s depending on the state of the control bits from the Micro-
Processor Interface and provided reference clock. For all of the architecture and clock distribution descriptions,
however, the standard SONET STS-48 rate of 2,488.32 Mbits/s (i.e., REFCLK_[P:N] = 155.52 MHz for the full rate
modes) is assumed.
Transmitter Architecture
The transmitter section accepts parallel data for transmission from the FPGA logic, formats it for transmission and
serializes the data. It also accepts the low-speed reference clock at the REFCLK input and uses this clock to syn-
thesize the internal high-speed serial bit clock. The serialized transmitted data are available at the differential CML
output pins to drive either an optical transmitters, coaxial media or a circuit board backplane.
The top level transmit architecture is shown in Figure 5. The main logical blocks in the transmit path are:
Output Port Controllers (OPCs) which contain the cell processing logic.
SONET processing logic.
Transmit SERDES and 32:8 MUX.
Depending on the mode of operation, the FPGA to backplane data path may include or bypass the various logical
blocks.
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