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| 型號： | M-ORSO82G52BM680-DB |
| 廠商： | LATTICE SEMICONDUCTOR CORP |
| 元件分類： | FPGA |
| 英文描述： | FPGA, 1296 CLBS, 333000 GATES, PBGA680 |
| 封裝： | PLASTIC, FBGA-680 |
| 文件頁數(shù)： | 41/123頁 |
| 文件大?。?/td> | 2207K |
| 代理商： | M-ORSO82G52BM680-DB |
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Lattice Semiconductor
ORCA ORSO82G5 Data Sheet
24
Applying too much preemphasis when it is not required, for example when driving a short backplane path, will also
degrade the data eye opening at the receiver. In the ORSO82G5, the degree of transmit preemphasis can be pro-
grammed per channel with two control register bits as shown in Table 4. The high-pass transfer function of the pre-
emphasis circuit is given by the following equation, where the value of a is shown in Table 4.
H(z) = (1 – az
–1)
Table 4. Preemphasis Settings
SERDES Receive Path
The receiver section receives high-speed serial data at its differential CML input port. These data are fed to the
clock recovery section which generates a recovered clock and retimes the data. Each SERDES receive channel
has its own PLL and this means that the receive clocks are asynchronous between channels. This also enables
each receive channel to either operate in half-rate or full-rate mode.The retimed data are deserialized and pre-
sented as a 8-bit parallel data on the output port. Two-phase receive byte clocks (RBC0 and RBC1) are available
synchronous with the parallel words. RBC0 has its rising edge aligned to the center of the receive byte. RBC1 has
its falling edge aligned to the center of the receive byte. The 8-bit data (LDOUT) as shown in Figure 10, changes on
a single clock edge (rising edge of RBC0 or falling edge of RBC1).
Figure 10. SERDES Receive Path Timing
The receive PLL has two modes of operation as follows: lock to reference and lock to data with retiming. When
setup to lock to data and no data or invalid data are present on the HDINP and HDINN pins, the receive VCO will
not lock to data and its frequency can drift outside of the nominal ±100 ppm range. Under this condition, the receive
PLL will lock to REFCLK for a xed time interval and then will attempt to lock to receive data. The process of
PE1
PE0
Amount of Preemphasis (a)
0
0% (No Preemphasis)
0
1
12.5%
1
0
12.5%
1
25%
.....
LDOUT[7:0]
RBC0x
RBC1x
q
7
r
1
r
0
s
7
p
3
p
2
p
1
p
0
.....
p
7
p
6
p
5
p
4
r
7
r
6
r
5
r
4
r
3
r
2
s
6
s
5
s
4
s
3
p
HDINx
LDOUT[7:0]
1-bit
8-bit
.....
LATENCY
p
q
r
s
SETUP
HOLD
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