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參數(shù)資料
| 型號： | M-ORSO82G52BM680-DB |
| 廠商： | LATTICE SEMICONDUCTOR CORP |
| 元件分類： | FPGA |
| 英文描述： | FPGA, 1296 CLBS, 333000 GATES, PBGA680 |
| 封裝： | PLASTIC, FBGA-680 |
| 文件頁數(shù)： | 47/123頁 |
| 文件大?。?/td> | 2207K |
| 代理商： | M-ORSO82G52BM680-DB |
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Lattice Semiconductor
ORCA ORSO82G5 Data Sheet
3
High-speed SERDES programmable serial data rates of 1.0 Gbits/s to 2.7 Gbits/s.
Asynchronous operation per receive channel (separate PLL per channel).
Transmit pre-emphasis (programmable) for improved receive data eye opening.
Provides a 10 Gbits/s backplane interface to switch fabric using four work and four protect 2.5 Gbit/s links. Also
supports port cards at rates between 1.0 Gbits/s and 2.7 Gbits/s.
Allows wide range of applications for SONET network termination, as well as generic data moving for high-speed
backplane data transfer.
No knowledge of SONET/SDH needed in generic applications. Simply supply data (125 MHz—
168.75 MHz clock) and optionally a frame pulse.
High-Speed Interface (HSI) function for clock/data recovery serial backplane data transfer without external
clocks.
Eight-channel HSI function provides 2.7 Gbits/s serial user data interface per channel for a total chip bandwidth
of >20 Gbits/s (full duplex).
SERDES has low-power CML buffers and support for 1.5 V/1.8 V I/Os.
SERDES HSI automatically recovers from loss-of-clock once its reference clock returns to normal operating
state.
Powerdown option of SERDES HSI receiver/transmitter on a per-channel basis.
Ability to mix half-rate and full-rate between the channels with the same reference clock.
Ability to congure each quad SERDES block independently with its own reference clock.
Programmable enable of SONET scrambler/descrambler.
Insertion and checking of link assignment values to facilitate interconnection and debugging of backplanes.
Optional AIS-L insertion during loss-of-frame.
Optional RDI-L insertion to indicate remote far-end defects for maintenance capabilities.
SPE signal marks payload bytes when cell processing is not used.
Frame alignment across multiple ORSO82G5 devices for work/protect switching at STS-768/STM-256 and
above rates.
In-band management and conguration through Transport OverHead (TOH) extraction/insertion.
Supports transparent mode where internally generated overhead bytes can be overridden by user-generated
overhead bytes from FPGA.
Optional A1A2 corruption, B1 byte corruption, and K2 byte corruption for system debug purposes.
Built-in boundary scan (IEEE 1149.1 and 1149.2 JTAG), including the SERDES interface.
FIFOs align incoming data across all eight channels (all eight channels, two groups of four channels, or four
groups of two channels). Optional ability to bypass alignment FIFOs for asynchronous operation between chan-
nels. (Each channel includes its own clock and frame pulse).
Optional cell processing blocks included. Cell processing includes cell creation, extraction, idle cell insertion and
deletion asynchronous from line rates. Four cell sizes supported:
– 77 bytes per cell (75 bytes of data payload)
– 81 bytes per cell (79 bytes of data payload)
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