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| 型號(hào)： | M-ORSO82G52BM680-DB |
| 廠商： | LATTICE SEMICONDUCTOR CORP |
| 元件分類： | FPGA |
| 英文描述： | FPGA, 1296 CLBS, 333000 GATES, PBGA680 |
| 封裝： | PLASTIC, FBGA-680 |
| 文件頁(yè)數(shù)： | 61/123頁(yè) |
| 文件大?。?/td> | 2207K |
| 代理商： | M-ORSO82G52BM680-DB |
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Lattice Semiconductor
ORCA ORSO82G5 Data Sheet
42
SONET Mode Octal Alignment
Figure 27 shows the clocking scheme for eight-channel alignment. In this application, all four clocks RSYSCLKA1,
RSYSCLKA2, RSYSCLKB1 and RSYSCLKB2 should be sourced from a common clock. Either RCK78A or
RCK78B can be used as a common clock source. The gure shows RCK78B being used as the clock source.
Figure 27. Receive Clocking for Octal Alignment
SPE Generator
The SPE generator is used to indicate the payload and overhead portions of a SONET frame. It is present in the
SONET data path only. The SPE generator generates row, column and sts counters based on the frame pulse
received from the (24 x 33) alignment FIFO or from the descrambler if alignment FIFOs are bypassed. It also
retimes the 32-bit data in order to align it with the SPE indicator. The SPE generator will also detect negative or
positive pointer justication (if justication is enabled) by looking at the ID bits in the H1 and H2 bytes and adjust
the SPE indicator for the STS-1 frame being justied as follows:
During positive pointer justication, the SPE will be low during H3 byte and the SPE byte following it.
During negative pointer justication, the SPE will be high during H3 byte.
During no justication, the SPE will be low during H3 byte.
This block only detects the incoming pointer bytes for SPE generation. This capability can be enabled by software
control. By default, the SPE generator will ignore any pointer justication. This block has no capability of any
pointer processing, pointer checking or pointer mover operation and ignores "New Data" indications from the
SONET specication.
SONET Mode Receive Timing
This section contains timing diagrams for major interfaces of this block to the FPGA logic when SONET frames are
to be transferred.
RBC0
RBC1
311.04 MHz
SERDES
2.488 Gbits/s
REFCLK[P,N]
(155.52 MHz)
DEMUX
RWCK[AA,AB,AC,AD] (77.76 MHz)
Framer,
descrambler
FPGA
32b
Cell
extractor
RxFIFO
IPC8/
160b
32b
other links in quad
RCK78A
SYSCLK156[A1,A2,8]
Alignment
FIFO
SPE
generator
RSYSCLK[A1,A2] (77.76)
RBC0
RBC1
311.04 MHz
SERDES
REFCLK[P,N]
(155.52 MHz)
DEMUX
RWCK[BA,BB,BC,BD] (77.76 MHz)
Framer,
descrambler
32b
Cell
extractor
RxFIFO
IPC8/
160b
32b
other links in quad
RCK78B
SYSCLK156[B1,B2,8]
Alignment
FIFO
SPE
generator
RSYSCLK[B1,B2 ] (77.76)
2.488 Gbits/s
Quad A
Quad B
IPC2
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