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| 型號(hào)： | M-ORSO82G52BM680-DB |
| 廠商： | LATTICE SEMICONDUCTOR CORP |
| 元件分類： | FPGA |
| 英文描述： | FPGA, 1296 CLBS, 333000 GATES, PBGA680 |
| 封裝： | PLASTIC, FBGA-680 |
| 文件頁(yè)數(shù)： | 32/123頁(yè) |
| 文件大小： | 2207K |
| 代理商： | M-ORSO82G52BM680-DB |
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Lattice Semiconductor
ORCA ORSO82G5 Data Sheet
16
The TOH block can performs A1/A2 corruption by inverting the A1/A2 bytes under software control. The block can
also force B1 errors by inverting the B1 byte or inject a fault indication by forcing the K2 byte to “00000110”. In the
receive direction, the errors will be detected and alarms set. In SONET mode, all TOH bytes can optionally be sent
transparently from the FPGA.
For each of the receive channels, the framer logic outputs 4 bytes (32-bits) of received data that are frame-aligned
and a frame pulse that is one clock-wide. The framer is responsible also for detecting the in-frame and Out-Of-
Frame status of the incoming data and sends out alarms (interrupts) on detecting an Out-Of-Frame (OOF) state.
In the transmit direction, the scrambler logic scrambles the outgoing data using the standard SONET polynomial 1
+ x
6 + x7. In the receive direction, the descrambler logic descrambles the incoming data using the same polynomial.
Multichannel Alignment FIFO and SPE Generation (for SONET mode)
In SONET mode, the incoming data on the 8 channels can be independent of one another or can be synchronized
in several ways. Two channels within a SERDES quad can be aligned together: channel A and B and/or channel C
and D. Alternately, all four channels in a SERDES quad can be aligned together to form a communication channel
with a bandwidth of 10 Gbits/s. Finally, the alignment can be extended across SERDES to align all 8 channels.
Individual channels within an alignment group can be disabled (i.e., power down) without disrupting other channels.
A disabled channel can also be aligned to its group without a disruption to the remaining channels. This holds true
only if the disabled channel had been previously enabled during alignments.
Cell Extraction, Striping and Destriping (for Cell Mode)
In the cell mode, cells are distributed across two-links or across eight-links. In the TX direction, cell data from the
FPGA are “striped” across links within a link group. Link groups can be in up to four two-link groups or one group of
eight-links. In the receive direction cell processing blocks extract cells from the link groups and send them to the
FPGA. This function is referred to as “destriping”.
Dual Port RAMs
There are two independent memory blocks in the core. Each memory block has a capacity of 4K words by 36 bits.
It has one read port, one write port, and four byte-write-enable (active-low) signals. The read data from the memory
block is registered so that it works as a pipelined synchronous memory block. These memory blocks are com-
pletely independent of the backplane driver blocks. They are only accessible from the FPGA logic and are not con-
nected to the system bus.
Loopback - Overview
There are two types of loopback that can be utilized inside the embedded core of the ORSO82G5, near end loop-
back and far end (line side) loopback. Both of these loopbacks are controlled by control registers inside the
ORSO82G5 core, which are accessible from the system bus and the MicroProcessor Interface (MPI).
FPSC Conguration - Overview
Conguration of the ORSO82G5 occurs in two stages: FPGA bit stream conguration and embedded core setup.
Prior to becoming operational, the FPGA goes through a sequence of states, including power-up, initialization, con-
guration, start-up, and operation. The FPGA logic is congured by standard FPGA bit stream conguration means
as discussed in the Series 4 FPGA data sheet.
The options for the embedded core are set via registers that are accessed through the FPGA system bus. The sys-
tem bus can be driven by an external PPC compliant microprocessor via the MPI block or via a user master inter-
face in FPGA logic. A simple IP block, that drives the system by using the user interface and uses very little FPGA
logic, is available in the MPI/System Bus application note (TN1017). This IP block sets up the embedded core via a
state machine and allows the ORSO82G5 to work in an independent system without an external MicroProcessor
Interface.
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