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| 型號(hào)： | M-ORSO82G52BM680-DB |
| 廠商： | LATTICE SEMICONDUCTOR CORP |
| 元件分類： | FPGA |
| 英文描述： | FPGA, 1296 CLBS, 333000 GATES, PBGA680 |
| 封裝： | PLASTIC, FBGA-680 |
| 文件頁(yè)數(shù)： | 75/123頁(yè) |
| 文件大小： | 2207K |
| 代理商： | M-ORSO82G52BM680-DB |
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Lattice Semiconductor
ORCA ORSO82G5 Data Sheet
55
A FIFO occupancy counter generates a RX_FIFO_OVRUN indication to the register interface if it detects a FIFO
overow condition. The cell mode allows for alignment of all eight-links or alignment of two-links. Thus there will be
2 IPC blocks for 2 pairs of channels per quad. Each of the twin-bundle IPC blocks will operate at 1/4 of 156MHz fre-
quency.
Input Port Controllers
The input port controllers (IPCs) are the block responsible for “directing trafc” for the ingress receive cell trafc
ow. The block diagrams for the 2-link and 8-link IPCs are shown in Figure 40. They provide the following essential
functions.
Determining when cell data can be read from the FIFOs of the individual links.
Insuring group bundles are properly aligned.
Scheduling reads from the RX FIFOs. Cells are read one at a time from the congured links.
Parsing the cell data into payload data (along with selected header information). Cells which have errors that
make them unusable (such as BIP or sequence number errors) are thrown away. This dropping of errored cells
can be disabled through register bits CELL_BIP_INH_xx and CELL_SEQ_INX_xx
Figure 40. IPC2 and IPC8 Block Diagrams
There are 5 IPC blocks in the embedded core. There is an IPC2 block for every channel pair:
IPC2_A1 combines links from channels AA,AB
IPC2_A2 combines links from channels AC,AD
RX
FIFO
IPC2
Block
IPC2_[A:B][1:2][0:39]
SYSCLK156[A:B][1:2]
32
77.76 MHz
RX
FIFO
32
77.76 MHz
RX
FIFO
IPC8
IPC8[0:159]
SYSCLK156 8
32
77.76 MHz
Cell
Extractor
RX
FIFO
32
77.76 MHz
LINK 0
LINK 1
LINK 0
LINK 7
40
160
FPGA
LOGIC
Block
FPGA
LOGIC
Cell
Extractor
Cell
Extractor
Cell
Extractor
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