參數(shù)資料
型號(hào)： LPC2919
廠商： NXP Semiconductors N.V.
元件分類： 32位微控制器
英文描述： ARM9 microcontroller with CAN and LIN
中文描述： 具有CAN和LIN的ARM9微控制器
文件頁(yè)數(shù)： 45/68頁(yè)
文件大?。?/td> 384K
代理商： LPC2919
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LPC2917_19_1
NXP B.V. 2007. All rights reserved.
Preliminary data sheet
Rev. 1.01 — 15 November 2007
45 of 68
NXP Semiconductors
LPC2917/19
ARM9 microcontroller with CAN and LIN
Clock Activity Detection:
Clocks that are inactive are automatically regarded as invalid,
and values of ’CLK_SEL’ that would select those clocks are masked and not written to the
control registers. This is accomplished by adding a clock detector to every clock
generator. The RDET register keeps track of which clocks are active and inactive, and the
appropriate ‘CLK_SEL’ values are masked and unmasked accordingly. Each clock
detector can also generate interrupts at clock activation and deactivation so that the
system can be notified of a change in internal clock status.
Clock detection is done using a counter running at the BASE_PCR_CLK frequency. If no
positive clock edge occurs before the counter has 32 cycles of BASE_PCR_CLK the clock
is assumed to be inactive. As BASE_PCR_CLK is slower than any of the clocks to be
detected, normally only one BASE_PCR_CLK cycle is needed to detect activity. After
reset all clocks are assumed to be ‘non-present’, so the RDET status register will be
correct only after 32 BASE_PCR_CLK cycles.
Note that this mechanism cannot protect against a currently-selected clock going from
active to inactive state. Therefore an inactive clock may still be sent to the system under
special circumstances, although an interrupt can still be generated to notify the system.
Glitch-Free Switching:
Provisions are included in the CGU to allow clocks to be
switched glitch-free, both at the output generator stage and also at secondary source
generators.
In the case of the PLL the clock will be stopped and held low for long enough to allow the
PLL to stabilize and lock before being re-enabled. For all non-PLL Generators the switch
will occur as quickly as possible, although there will always be a period when the clock is
held low due to synchronization requirements.
If the current clock is high and does not go low within 32 cycles of BASE_PCR_CLK it is
assumed to be inactive and is asynchronously forced low. This prevents deadlocks on the
interface.
8.8.4.3
PLL functional description
A block diagram of the PLL is shown in
Figure 14
. The input clock is fed directly to the
analog section. This block compares the phase and frequency of the inputs and generates
the main clock
2
. These clocks are either divided by 2*P by the programmable post divider
to create the output clock, or sent directly to the output. The main output clock is then
divided by M by the programmable feedback divider to generate the feedback clock. The
output signal of the analog section is also monitored by the lock detector to signal when
the PLL has locked onto the input clock.
2.
Generation of the main clock is restricted by the frequency range of the PLL clock input. See
Table 31
, Dynamic characteristics.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
LPC2919/01 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:ARM9 microcontroller with CAN and LIN
LPC2919FBD144 制造商:NXP Semiconductors 功能描述:IC MCU 32BIT ARM968 SMD LQFP144
LPC2919FBD144,551 功能描述:ARM微控制器 - MCU ARM968 768K FL/48K RAM LIN 2.0 RoHS:否 制造商:STMicroelectronics 核心:ARM Cortex M4F 處理器系列:STM32F373xx 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:72 MHz 程序存儲(chǔ)器大小:256 KB 數(shù)據(jù) RAM 大小:32 KB 片上 ADC:Yes 工作電源電壓:1.65 V to 3.6 V, 2 V to 3.6 V, 2.2 V to 3.6 V 工作溫度范圍:- 40 C to + 85 C 封裝 / 箱體:LQFP-48 安裝風(fēng)格:SMD/SMT
LPC2919FBD144/01 制造商:NXP Semiconductors 功能描述:MCU, 32BIT, ARM968E-S, 125MHZ, LQFP-144 制造商:NXP Semiconductors 功能描述:MCU, 32BIT, ARM968E-S, 125MHZ, LQFP-144, Controller Family/Series:LPC2900, Core Size:32bit, No. of I/O's:108, Supply Voltage Min:1.71V, Supply Voltage Max:1.89V, Digital IC Case Style:LQFP, No. of Pins:144, Program Memory Size:768KB,
LPC2919FBD144/01/ 制造商:NXP Semiconductors 功能描述:MCU ARM9 144LQFP
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