參數(shù)資料
型號(hào): LPC2919
廠(chǎng)商: NXP Semiconductors N.V.
元件分類(lèi): 32位微控制器
英文描述: ARM9 microcontroller with CAN and LIN
中文描述: 具有CAN和LIN的ARM9微控制器
文件頁(yè)數(shù): 44/68頁(yè)
文件大?。?/td> 384K
代理商: LPC2919
FDIV0..6
DRAFTDRAFTDRAFTDRAFTDRAFTDRAFTD
LPC2917_19_1
NXP B.V. 2007. All rights reserved.
Preliminary data sheet
Rev. 1.01 — 15 November 2007
44 of 68
NXP Semiconductors
LPC2917/19
ARM9 microcontroller with CAN and LIN
Any output generator (except for BASE_SAFE_CLK and BASE_PCR_CLK) can be
connected to either a fractional divider (FDIV0..6) or to one of the outputs of the PLL or to
LP_OSC/crystal oscillator directly. BASE_SAFE_CLK and BASE_PCR_CLK can use only
LP_OSC as source.
The fractional dividers can be connected to one of the outputs of the PLL or directly to
LP_OSC/crystal Oscillator.
The PLL can be connected to the crystal oscillator.
In this way every output generating the base clocks can be configured to get the required
clock. Multiple output generators can be connected to the same primary or secondary
clock source, and multiple secondary clock sources can be connected to the same PLL
output or primary clock source.
Invalid selections/programming - connecting the PLL to an FDIV or to one of the PLL
outputs itself for example - will be blocked by hardware. The control register will not be
written, the previous value will be kept, although all other fields will be written with new
data. This prevents clocks being blocked by incorrect programming.
Default Clock Sources:
Every secondary clock generator or output generator is
connected to LP_OSC at reset. In this way the device runs at a low frequency after reset.
It is recommended to switch BASE_SYS_CLK to a high-frequency clock generator as
(one of) the first step(s) in the boot code after verifying that the high-frequency clock
generator is running.
Fig 13. Structure of the clock generation scheme
PLL160M
XO50M
OSC1M
Clock
outputs
clkout /
clkout120 /
clkout240
Output
Control
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