參數(shù)資料
型號： LMK04001BISQE/NOPB
廠商： National Semiconductor
文件頁數(shù)： 7/65頁
文件大小： 0K
描述： IC CLOCK COND 1.5GHZ W/PLL 48LLP
標準包裝： 1
系列： PowerWise®
類型： 時鐘調(diào)節(jié)器
PLL： 是
輸入： LVCMOS
輸出： LVCMOS，2VPECL，LVPECL
電路數(shù)： 1
比率 - 輸入:輸出： 2:7
差分 - 輸入:輸出： 是/是
頻率 - 最大： 1.57GHz
除法器/乘法器： 是/是
電源電壓： 3.15 V ~ 3.45 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 48-WFQFN 裸露焊盤
供應商設備封裝： 48-LLP（7x7）
包裝： 標準包裝
產(chǎn)品目錄頁面： 1275 (CN2011-ZH PDF)
其它名稱： LMK04001BISQEDKR
SNOSAZ8J – SEPTEMBER 2008 – REVISED SEPTEMBER 2011
Electrical Characteristics (continued)
(3.15 V
≤ VCC ≤ 3.45 V, -40 °C ≤ TA ≤ 85 °C. Typical values represent most likely parametric norms at VCC = 3.3 V, TA = 25
°C, at the Recommended Operating Conditions at the time of product characterization and are not guaranteed.)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
LMK040x0 (25) (26)
BW = 12 kHz to 20 MHz
140
200
fCLKout = 250 MHz
BW = 100 Hz to 20 MHz
185
Integrated RMS Jitter
LMK040x1 (27) (26)
BW = 12 kHz to 20 MHz
130
200
fCLKout = 250 MHz
BW = 100 Hz to 20 MHz
190
Integrated RMS Jitter
JCLKout
fs
LVPECL/2VPECL
LMK040x2 (28) (26)
BW = 12 kHz to 20 MHz
150
200
fCLKout = 250 MHz
BW = 100 Hz to 20 MHz
190
Integrated RMS Jitter
LMK040x3 (29) (26)
BW = 12 kHz to 20 MHz
145
200
fCLKout = 250 MHz
BW = 100 Hz to 20 MHz
200
Integrated RMS Jitter
LMK040x1 (30)
BW = 12 kHz to 20 MHz
130
fCLKout = 250 MHz
BW = 100 Hz to 20 MHz
190
Integrated RMS Jitter
JCLKout
fs
LVDS
LMK040x3 (31)
BW = 12 kHz to 20 MHz
145
fCLKout = 250 MHz
BW = 100 Hz to 20 MHz
200
Integrated RMS Jitter
(25) For LMK040x0, FVCO = 1250 MHz. PLL1 parameters: FDET = 1 MHz, ICP1 = 100 A, loop bandwidth = 20 Hz. A 100 MHz VCXO drives
the OSCin input of PLL2. PLL2 parameters: VCO_DIV = 5, N2 = 5, R2 = 2, FDET = 50 MHz, ICP2 = 3.2 mA, C1 = 0 pF, C2 = 12 nF, R2
= 1.8 k
Ω, LBW = 254 kHz, PM = 81°. CLKDIST parameters: CLKoutX_DIV = Bypass, CLKout_DLY = OFF. VCXO phase noise: 100 Hz:
-100 dBc/Hz; 1 kHz: -128 dBc/Hz; 10 kHz: -144 dBc/Hz; 100 kHz: -147 dBc/Hz.
(26) Max jitter specification applies to CH3 (LVPECL) output and guaranteed by test in production.
(27) For LMK040x1, FVCO = 1500 MHz. PLL1 parameters: FDET = 1 MHz, ICP1 = 100 A, loop bandwidth = 20 Hz. A 100 MHz VCXO drives
the OSCin input of PLL2. PLL2 parameters: VCO_DIV = 3, N2 = 5, R2 = 1, FDET = 100 MHz, ICP2 = 1.6 mA, C1 = 0 pF, C2 = 12 nF, R2
= 1.8 k
Ω, LBW = 271 kHz, PM = 80°. CLKDIST parameters: CLKoutX_DIV = 2, CLKout_DLY = OFF. VCXO phase noise: 100 Hz: -100
dBc/Hz; 1 kHz: -128 dBc/Hz; 10 kHz: -144 dBc/Hz; 100 kHz: -147 dBc/Hz.
(28) For LMK040x2, FVCO = 1750 MHz. PLL1 parameters: FDET = 1 MHz, ICP1 = 100 A, loop bandwidth = 20 Hz. A 100 MHz VCXO drives
the OSCin input of PLL2. PLL2 parameters: VCO_DIV = 7, N2 = 5, R2 = 2, FDET = 50 MHz, ICP2 = 3.2 mA, C1 = 0 pF, C2 = 12 nF, R2
= 1.8 k
Ω, LBW = 360 kHz, PM = 79°. CLKDIST parameters: CLKoutX_DIV = Bypass, CLKout_DLY = OFF. VCXO phase noise: 100 Hz:
-100 dBc/Hz; 1 kHz: -128 dBc/Hz; 10 kHz: -144 dBc/Hz; 100 kHz: -147 dBc/Hz.
(29) For LMK040x3, FVCO = 2000 MHz. PLL1 parameters: FDET = 1 MHz, ICP1 = 100 A, loop bandwidth = 20 Hz. A 100 MHz VCXO drives
the OSCin input of PLL2. PLL2 parameters: VCO_DIV = 2, N2 = 10, R2 = 1, FDET = 100 MHz, ICP2 = 1.6 mA, C1 = 0 pF, C2 = 12 nF,
R2 = 1.8 k
Ω, LBW = 445 kHz, PM = 76°. CLKDIST parameters: CLKoutX_DIV = 4, CLKout_DLY = OFF. VCXO phase noise: 100 Hz: -
100 dBc/Hz; 1 kHz: -128 dBc/Hz; 10 kHz: -144 dBc/Hz; 100 kHz: -147 dBc/Hz.
(30) For LMK040x1, FVCO = 1500 MHz. PLL1 parameters: FDET = 1 MHz, ICP1 = 100 A, loop bandwidth = 20 Hz. A 100 MHz VCXO drives
the OSCin input of PLL2. PLL2 parameters: VCO_DIV = 3, N2 = 5, R2 = 1, FDET = 100 MHz, ICP2 = 1.6 mA, C1 = 0 pF, C2 = 12 nF, R2
= 1.8 k
Ω, LBW = 271 kHz, PM = 80°. CLKDIST parameters: CLKoutX_DIV = 2, CLKout_DLY = OFF. VCXO phase noise: 100 Hz: -100
dBc/Hz; 1 kHz: -128 dBc/Hz; 10 kHz: -144 dBc/Hz; 100 kHz: -147 dBc/Hz.
(31) For LMK040x3, FVCO = 2000 MHz. PLL1 parameters: FDET = 1 MHz, ICP1 = 100 A, loop bandwidth = 20 Hz. A 100 MHz VCXO drives
the OSCin input of PLL2. PLL2 parameters: VCO_DIV = 2, N2 = 10, R2 = 1, FDET = 100 MHz, ICP2 = 1.6 mA, C1 = 0 pF, C2 = 12 nF,
R2 = 1.8 k
Ω, LBW = 445 kHz, PM = 76°. CLKDIST parameters: CLKoutX_DIV = 4, CLKout_DLY = OFF. VCXO phase noise: 100 Hz: -
100 dBc/Hz; 1 kHz: -128 dBc/Hz; 10 kHz: -144 dBc/Hz; 100 kHz: -147 dBc/Hz.
Copyright 2008–2011, Texas Instruments Incorporated
15
相關PDF資料
PDF描述
M83723/86G10206 CONN PLUG 2POS STRAIGHT W/SCKT
MS27472E18A53S CONN RCPT 53POS WALL MT W/SCKT
CS3106A-32-73P CONN PLUG 46POS STRAIGHT W/PINS
LMK04000BISQE/NOPB IC CLOCK COND 1.2GHZ W/PLL 48LLP
VE-B4W-MV CONVERTER MOD DC/DC 5.5V 150W
相關代理商/技術參數(shù)
參數(shù)描述
LMK04001BISQX 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Low-Noise Clock Jitter Cleaner with Cascaded PLLs
LMK04001BISQX/NOPB 功能描述:時鐘合成器/抖動清除器 RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel
LMK04002BEVAL 功能描述:時鐘和定時器開發(fā)工具 LMK04002 EVAL BOARD RoHS:否 制造商:Texas Instruments 產(chǎn)品:Evaluation Modules 類型:Clock Conditioners 工具用于評估:LMK04100B 頻率:122.8 MHz 工作電源電壓:3.3 V
LMK04002BEVAL/NOPB 功能描述:BOARD EVAL FOR LMK04002B RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估演示板和套件 系列:PowerWise® 標準包裝:1 系列:- 主要目的:數(shù)字電位器 嵌入式:- 已用 IC / 零件:AD5258 主要屬性:- 次要屬性:- 已供物品:板 相關產(chǎn)品:AD5258BRMZ1-ND - IC POT DGTL I2C1K 64P 10MSOPAD5258BRMZ10-ND - IC POT DGTL I2C 10K 64P 10MSOPAD5258BRMZ100-ND - IC POT DGTL I2C 100K 64P 10MSOPAD5258BRMZ50-ND - IC POT DGTL I2C 50K 64P 10MSOPAD5258BRMZ1-R7-ND - IC POT DGTL I2C 1K 64P 10MSOPAD5258BRMZ10-R7-ND - IC POT DGTL I2C 10K 64P 10MSOPAD5258BRMZ50-R7-ND - IC POT DGTL I2C 50K 64P 10MSOPAD5258BRMZ100-R7-ND - IC POT DGTL I2C 100K 64P 10MSOP
LMK04002BISQ 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Low-Noise Clock Jitter Cleaner with Cascaded PLLs
發(fā)布緊急采購，3分鐘左右您將得到回復。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*