參數(shù)資料
型號: LMK04001BISQE/NOPB
廠商: National Semiconductor
文件頁數(shù): 37/65頁
文件大小: 0K
描述: IC CLOCK COND 1.5GHZ W/PLL 48LLP
標準包裝: 1
系列: PowerWise®
類型: 時鐘調(diào)節(jié)器
PLL:
輸入: LVCMOS
輸出: LVCMOS,2VPECL,LVPECL
電路數(shù): 1
比率 - 輸入:輸出: 2:7
差分 - 輸入:輸出: 是/是
頻率 - 最大: 1.57GHz
除法器/乘法器: 是/是
電源電壓: 3.15 V ~ 3.45 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 48-WFQFN 裸露焊盤
供應商設備封裝: 48-LLP(7x7)
包裝: 標準包裝
產(chǎn)品目錄頁面: 1275 (CN2011-ZH PDF)
其它名稱: LMK04001BISQEDKR
SNOSAZ8J – SEPTEMBER 2008 – REVISED SEPTEMBER 2011
Register 15
PLL2_N: PLL2_N Counter
The PLL2_N Counter is 18 bits wide. It divides the output of the VCO Divider and is connected to the PLL2
Phase Detector. Each time the PLL2_N Counter value is updated via the uWire interface, an internal algorithm is
triggered that optimizes the VCO performance.
Table 30. PLL2_N: PLL2_N Counter Values
N [17:0]
VALUE
b17
b16
...
b6
b5
b4
b3
b2
b1
b0
0
...
0
Not Valid
0
1
0
1
0
2
.
...
1
262143
PLL2_CP_GAIN: PLL2 Charge Pump Current and Output Control
The PLL2 charge pump output current level is controlled with the PLL2_CP_GAIN register. The following table
presents the charge pump current control values.
Table 31. PLL2_CP_GAIN: PLL2 Charge Pump Current Selections
PLL2_CP_GAIN [1:0]
CP_TRI
Charge Pump Current (A)
b1
b0
X
1
Hi-Z
0
100
0
1
0
400
1
0
1600
1
0
3200
VCO_DIV: PLL2 VCO Divide Register
A divider is provided on the output of the PLL2 VCO to enable a wide range of output clock frequencies. The
output of this divider is placed on the input path for the clock distribution section, which feeds each of the
individual clock channels. The divider provides integer divide ratios from 2 to 8.
Table 32. VCO_DIV: PLL2 VCO Divider Values
VCO_DIV [3:0]
Divide Value
b3
b2
b1
b0
0
Invalid
0
1
Invalid
0
1
0
2
0
1
3
0
1
0
4
0
1
0
1
5
0
1
0
6
0
1
7
1
0
8
42
Copyright 2008–2011, Texas Instruments Incorporated
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