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參數(shù)資料
| 型號(hào)： | LMK04001BISQE/NOPB |
| 廠商： | National Semiconductor |
| 文件頁數(shù)： | 17/65頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLOCK COND 1.5GHZ W/PLL 48LLP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | PowerWise® |
| 類型： | 時(shí)鐘調(diào)節(jié)器 |
| PLL： | 是 |
| 輸入： | LVCMOS |
| 輸出： | LVCMOS，2VPECL，LVPECL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 2:7 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 1.57GHz |
| 除法器/乘法器： | 是/是 |
| 電源電壓： | 3.15 V ~ 3.45 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-WFQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 48-LLP（7x7） |
| 包裝： | 標(biāo)準(zhǔn)包裝 |
| 產(chǎn)品目錄頁面： | 1275 (CN2011-ZH PDF) |
| 其它名稱： | LMK04001BISQEDKR |
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SNOSAZ8J – SEPTEMBER 2008 – REVISED SEPTEMBER 2011
FEATURES
System Architecture
The cascaded PLL architecture of the LMK040xx was chosen to provide the lowest jitter performance over the
widest range of output frequencies and phase noise offset frequencies. The first stage PLL (PLL1) is used in
conjunction with an external reference clock and an external VCXO to provide a frequency accurate, low phase
noise reference clock for the second stage frequency multiplication PLL (PLL2). PLL1 typically uses a narrow
loop bandwidth (10 Hz to 200 Hz) to retain the frequency accuracy of the reference clock input signal while at the
same time suppressing the higher offset frequency phase noise that the reference clock may have accumulated
along its path or from other circuits. The “cleaned” reference clock frequency accuracy is combined with the low
phase noise of an external VCXO to provide the reference input to PLL2. The low phase noise reference
provided to PLL2 allows it to use wider loop bandwidths (50 kHz to 200 kHz). The chosen loop bandwidth for
PLL2 should take best advantage of the superior high offset frequency phase noise profile of the internal VCO
and the good low offset frequency phase noise of the reference VCXO for PLL2. Ultra low jitter is achieved by
allowing the external VCXO’s phase noise to dominate the final output phase noise at low offset frequencies and
the internal VCO’s phase noise to dominate the final output phase noise at high offset frequencies. This results in
best overall phase noise and jitter performance.
Redundant Reference Inputs (CLKin0/CLKin0*, CLKin1/CLKin1*)
The LMK040xx has two LVDS/LVPECL/LVCMOS compatible reference clock inputs for PLL1, CLKin0 and
CLKin1. The selection of the preferred input may be fixed to either CLKin0 or CLKin1, or may be configured to
employ one of two automatic switching modes when redundant clock signals are present. The PLL1 reference
clock input buffers may also be individually configured as either a CMOS buffered input or a bipolar buffered
input.
PLL1 CLKinX (X=0,1) LOSS OF SIGNAL (LOS)
When either of the two auto-switching modes is selected for the reference clock input mode, the signal status of
the selected reference clock input is indicated by the state of the CLKinX_LOS (loss-of-signal) output. These
outputs may be configured as either CMOS (active HIGH on loss-of-signal), NMOS open-drain or PMOS open-
drain. If PLL1 was originally locked and then both reference clocks go away, then the frequency accuracy of the
LMK04000 device will be set by the absolute tuning range of the VCXO used on PLL1. The absolute tuning
range of the VCXO can be determined by multiplying its' tuning constant by the charge pump voltage.
Integrated Loop Filter Poles
The LMK040xx features programmable 3rd and 4th order loop filter poles for PLL2. When enabled, internal
resistors and capacitor values may be selected from a fixed range of values to achieve either 3rd or 4th order
loop filter response. These programmable components compliment external components mounted near the chip.
Clock Distribution
The LMK040xx features a clock distribution block with a minimum of five outputs that are a mixture of LVPECL,
2VPECL, LVDS, and LVCMOS. The exact combination is determined by the part number. The 2VPECL is a
National Semiconductor proprietary configuration that produces a 2 Vpp differential swing for compatibility with
many data converters. More than five outputs may be available for device versions that offer dual LVCMOS
outputs.
CLKout Divide (CLKoutX_DIV, X = 0 to 4)
Each individual clock distribution channel includes a channel divider. The range of divide values is 2 to 510, in
steps of 2. “Bypass” mode operates as a divide-by-1.
CLKout Delay (CLKoutX_DLY, X = 0 to 4)
Each individual clock distribution channel includes a delay adjustment. Clock output delay registers
(CLKoutX_DLY) support a nominal 150 ps step size and range from 0 to 2250 ps of total delay.
24
Copyright 2008–2011, Texas Instruments Incorporated
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