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參數(shù)資料
| 型號： | LMK04001BISQE/NOPB |
| 廠商： | National Semiconductor |
| 文件頁數(shù)： | 42/65頁 |
| 文件大小： | 0K |
| 描述： | IC CLOCK COND 1.5GHZ W/PLL 48LLP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | PowerWise® |
| 類型： | 時(shí)鐘調(diào)節(jié)器 |
| PLL： | 是 |
| 輸入： | LVCMOS |
| 輸出： | LVCMOS，2VPECL，LVPECL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 2:7 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 1.57GHz |
| 除法器/乘法器： | 是/是 |
| 電源電壓： | 3.15 V ~ 3.45 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-WFQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 48-LLP（7x7） |
| 包裝： | 標(biāo)準(zhǔn)包裝 |
| 產(chǎn)品目錄頁面： | 1275 (CN2011-ZH PDF) |
| 其它名稱： | LMK04001BISQEDKR |
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0.33 mm, typ
1.2 mm, typ
5.0 mm, min
SNOSAZ8J – SEPTEMBER 2008 – REVISED SEPTEMBER 2011
Power Supply Conditioning
The recommended technique for power supply management is to connect the power pins for the clock outputs
(pins 13, 37, 40, 43, and 46) to a dedicated power plane and connect all other power pins on the device (pins 3,
8, 18, 19, 22, 24, 30, 31, and 33) to a second power plane. Note: the LMK04000 family has internal voltage
regulators for the PLL and VCO blocks to provide noise immunity.
Thermal Management
Power consumption of the LMK04000 family of devices can be high enough to require attention to thermal
management. For reliability and performance reasons the die temperature should be limited to a maximum of
125 °C. That is, as an estimate, TA (ambient temperature) plus device power consumption times θJA should not
exceed 125 °C.
The package of the device has an exposed pad that provides the primary heat removal path as well as excellent
electrical grounding to a printed circuit board. To maximize the removal of heat from the package a thermal land
pattern including multiple vias to a ground plane must be incorporated on the PCB within the footprint of the
package. The exposed pad must be soldered down to ensure adequate heat conduction out of the package. A
recommended land and via pattern is shown in Figure 15. More information on soldering WQFN packages can
be obtained: http://www.national.com/analog/packaging/.
Figure 15. Recommended Land and Via Pattern
To minimize junction temperature it is recommended that a simple heat sink be built into the PCB (if the ground
plane layer is not exposed). This is done by including a copper area of about 2 square inches on the opposite
side of the PCB from the device. This copper area may be plated or solder coated to prevent corrosion but
should not have conformal coating (if possible), which could provide thermal insulation. The vias shown in
Figure 15 should connect these top and bottom copper layers and to the ground layer. These vias act as “heat
pipes” to carry the thermal energy away from the device side of the board to where it can be more effectively
dissipated.
Copyright 2008–2011, Texas Instruments Incorporated
47
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| LMK04001BISQX | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Low-Noise Clock Jitter Cleaner with Cascaded PLLs |
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| LMK04002BEVAL/NOPB | 功能描述:BOARD EVAL FOR LMK04002B RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估演示板和套件 系列:PowerWise® 標(biāo)準(zhǔn)包裝:1 系列:- 主要目的:數(shù)字電位器 嵌入式:- 已用 IC / 零件:AD5258 主要屬性:- 次要屬性:- 已供物品:板 相關(guān)產(chǎn)品:AD5258BRMZ1-ND - IC POT DGTL I2C1K 64P 10MSOPAD5258BRMZ10-ND - IC POT DGTL I2C 10K 64P 10MSOPAD5258BRMZ100-ND - IC POT DGTL I2C 100K 64P 10MSOPAD5258BRMZ50-ND - IC POT DGTL I2C 50K 64P 10MSOPAD5258BRMZ1-R7-ND - IC POT DGTL I2C 1K 64P 10MSOPAD5258BRMZ10-R7-ND - IC POT DGTL I2C 10K 64P 10MSOPAD5258BRMZ50-R7-ND - IC POT DGTL I2C 50K 64P 10MSOPAD5258BRMZ100-R7-ND - IC POT DGTL I2C 100K 64P 10MSOP |
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