參數資料
型號: LMK04001BISQE/NOPB
廠商: National Semiconductor
文件頁數: 45/65頁
文件大小: 0K
描述: IC CLOCK COND 1.5GHZ W/PLL 48LLP
標準包裝: 1
系列: PowerWise®
類型: 時鐘調節(jié)器
PLL:
輸入: LVCMOS
輸出: LVCMOS,2VPECL,LVPECL
電路數: 1
比率 - 輸入:輸出: 2:7
差分 - 輸入:輸出: 是/是
頻率 - 最大: 1.57GHz
除法器/乘法器: 是/是
電源電壓: 3.15 V ~ 3.45 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 48-WFQFN 裸露焊盤
供應商設備封裝: 48-LLP(7x7)
包裝: 標準包裝
產品目錄頁面: 1275 (CN2011-ZH PDF)
其它名稱: LMK04001BISQEDKR
SNOSAZ8J – SEPTEMBER 2008 – REVISED SEPTEMBER 2011
PIN DESCRIPTIONS (continued)
Pin Number
Name(s)
I/O
Type
Description
19
VCC5
PWR
Power Supply for CLKin buffers and PLL1 R-divider
20
CLKin0
I
ANLG
Reference Clock Input Port for PLL1 - AC or DC
Coupled (1)
21
CLKin0*
I
ANLG
Reference Clock Input Port for PLL1 (complimentary) -
AC or DC Coupled (1)
22
VCC6
PWR
Power Supply for PLL1 Phase Detector and Charge
Pump
23
CPout1
O
ANLG
Charge Pump1 Output
24
VCC7
PWR
Power Supply for PLL1 N-Divider
25
CLKin1
I
ANLG
Reference Clock Input Port for PLL1 - AC or DC
Coupled (1)
26
CLKin1*
I
ANLG
Reference Clock Input Port for PLL1 (complimentary) -
AC or DC Coupled (1)
27
SYNC*
I
CMOS
Global Clock Output Synchronization
28
OSCin
I
ANLG
Reference oscillator Input for PLL2 - AC Coupled
29
OSCin*
I
ANLG
Reference oscillator Input for PLL2 - AC Coupled
30
VCC8
PWR
Power Supply for OSCin Buffer and PLL2 R-Divider
31
VCC9
PWR
Power Supply for PLL2 Phase Detector and Charge
Pump
32
CPout2
O
ANLG
Charge Pump2 Output
33
VCC10
PWR
Power Supply for VCO Divider and PLL2 N-Divider
34
CLKin0_LOS
O
LVCMOS
Status of CLKin0 reference clock input
35
CLKin1_LOS
O
LVCMOS
Status of CLKin1 reference clock input
36
Bias
I
ANLG
Bias Bypass. AC coupled with 1 F capacitor to Vcc1
37
VCC11
PWR
Power Supply for CLKout1
38
CLKout1
O
LVPECL/LVCMOS
Clock Channel 1 Output
39
CLKout1*
O
LVPECL/LVCMOS
Clock Channel 1* Output
40
VCC12
PWR
Power Supply for CLKout2
41
CLKout2
O
LVPECL/LVCMOS
Clock Channel 2 Output
42
CLKout2*
O
LVPECL/LVCMOS
Clock Channel 2* Output
43
VCC13
PWR
Power Supply for CLKout3
44
CLKout3
O
LVPECL
Clock Channel 3 Output
45
CLKout3*
O
LVPECL
Clock Channel 3* Output
46
VCC14
PWR
Power Supply for CLKout4
47
CLKout4
O
LVDS/LVPECL
Clock Channel 4 Output
48
CLKout4*
O
LVDS/LVPECL
Clock Channel 4* Output
DAP
DIE ATTACH PAD, connect to GND
(1)
The reference clock inputs may be either AC or DC coupled.
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Copyright 2008–2011, Texas Instruments Incorporated
5
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