參數(shù)資料
型號： LMK04001BISQE/NOPB
廠商： National Semiconductor
文件頁數(shù)： 53/65頁
文件大?。?/td> 0K
描述： IC CLOCK COND 1.5GHZ W/PLL 48LLP
標準包裝： 1
系列： PowerWise®
類型： 時鐘調(diào)節(jié)器
PLL： 是
輸入： LVCMOS
輸出： LVCMOS，2VPECL，LVPECL
電路數(shù)： 1
比率 - 輸入:輸出： 2:7
差分 - 輸入:輸出： 是/是
頻率 - 最大： 1.57GHz
除法器/乘法器： 是/是
電源電壓： 3.15 V ~ 3.45 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 48-WFQFN 裸露焊盤
供應商設(shè)備封裝： 48-LLP（7x7）
包裝： 標準包裝
產(chǎn)品目錄頁面： 1275 (CN2011-ZH PDF)
其它名稱： LMK04001BISQEDKR
100
1000
10000
100000
OFFSET (Hz)
-170
-160
-150
-140
-130
-120
-110
-100
-90
-80
d
Bc
1000000
10000000
100000000
s yK
^ _, RMS jitter = 224 fs
s yK
^ _, RMS jitter = 167 fs
100
1000
10000
100000
OFFSET (Hz)
-170
-160
-150
-140
-130
-120
-110
-100
-90
-180
d
Bc
1000000
10000000
100000000
s yK
^ _
s yK
^ _
SNOSAZ8J – SEPTEMBER 2008 – REVISED SEPTEMBER 2011
Figure 32. VCXO Phase Noise Comparison, 100 MHz
This plot shows that VCXO “B” exhibits superior phase noise when compared to VCXO “A”. Both VCXOs offer
excellent jitter performance from 100 Hz to 200 kHz. VCXO “A” exhibits RMS jitter of 151 femtoseconds (fs),
while VCXO “B” has RMS jitter of 90 fs.
Figure 33 Figure 34 Figure 35 present a side-by-side comparison of clock output phase noise at 250 MHz,
organized by output format and associated VCXO. The total RMS jitter listed on the plots is integrated from 100
Hz to 20 MHz. Examining these plots, the clock output phase noise associated with VCXO “B” is superior in all
cases. The average improvement in RMS jitter due to VCXO “B” is approximately 47 fs. The plots show the
primary difference in clock output phase noise is in the band from 100 Hz to approximately 4 kHz. Across this
range, the VCXO phase noise dominates that of the PLL, given the loop bandwidth of this design, which is 152
kHz. Above 4 kHz, the PLL noise dominates (inside the loop bandwidth), so it is basically the same for either
VCXO. Comparing the jitter of two VCXOs in the 100 Hz to 4 kHz band, it can be shown that VCXO “A” exhibits
jitter of 142 fs, and VCXO “B” exhibits jitter of 90 fs. The difference, 52 fs, accounts for the majority of the
average difference in RMS jitter at the clock outputs when comparing VCXOs.
The PLL configurations listed below were the same for both VCXOs/LMK040xx pair:
PLL1 loop filter components: C1 = 100 nF, C2 = 680 nF, R2 = 39 k
Ω
PLL1 fPD = 1 MHz, CP gain = 100 A, loop BW = 20 Hz
PLL2 loop filter components: C1 = 0, C2 = 12 nF, R2 = 1.8 k
Ω
PLL2 fPD = 25 MHz, CP gain = 3200 A, loop BW = 152 kHz
Figure 33. LVDS Clock Output Phase Noise Comparison, 250 MHz
Copyright 2008–2011, Texas Instruments Incorporated
57
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