X FOSCin (VCO_DIV
參數(shù)資料
型號(hào)： LMK04001BISQE/NOPB
廠商： National Semiconductor
文件頁(yè)數(shù)： 28/65頁(yè)
文件大?。?/td> 0K
描述： IC CLOCK COND 1.5GHZ W/PLL 48LLP
標(biāo)準(zhǔn)包裝： 1
系列： PowerWise®
類(lèi)型： 時(shí)鐘調(diào)節(jié)器
PLL： 是
輸入： LVCMOS
輸出： LVCMOS，2VPECL，LVPECL
電路數(shù)： 1
比率 - 輸入:輸出： 2:7
差分 - 輸入:輸出： 是/是
頻率 - 最大： 1.57GHz
除法器/乘法器： 是/是
電源電壓： 3.15 V ~ 3.45 V
工作溫度： -40°C ~ 85°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 48-WFQFN 裸露焊盤(pán)
供應(yīng)商設(shè)備封裝： 48-LLP（7x7）
包裝： 標(biāo)準(zhǔn)包裝
產(chǎn)品目錄頁(yè)面： 1275 (CN2011-ZH PDF)
其它名稱(chēng)： LMK04001BISQEDKR
N
R
X FOSCin
(VCO_DIV CLK_DIV)
FCLK error =
N
R
FOSCin
(VCO_DIV CLK_DIV)
FCLK =
SNOSAZ8J – SEPTEMBER 2008 – REVISED SEPTEMBER 2011
CLKoutX_MUX: Clock Output Mux
The output of each CLKoutX channel pair is controlled by its' channel multiplexer (mux). The mux can select
between several signals: bypassed, divided only, divided and delayed, or delayed only.
Table 10. CLKoutX_MUX: Clock Channel Multiplexer Control Bits
CLKout_MUX [1:0]
Clock Mode
b1
b0
0
Bypassed
0
1
Divided
1
0
Delayed
1
Divided and Delayed
Registers 5, 6
These registers are reserved. These register values should not be modified from the values shown in the register
map.
Register 7
Reset bit
This bit is only in register R7. The use of this bit is optional and it should be set to '0' if not used. Setting this bit
to a '1' forces all registers to their power on reset condition and therefore automatically clears this bit.
Registers 8, 9
These registers are reserved. These register values should not be modified from the values shown in the register
map.
Register 10
RC_DLD1_Start: PLL1 Digital Lock Detect Run Control bit
This bit is used to control the state machine for the PLL2 VCO tuning algorithm. The following table describes the
function of this bit.
Table 11. RC_DLD1_Start bit States
RC_DLD1_Start
Description
1
The PLL2 VCO tuning algorithm trigger is delayed until PLL1 Digital Lock Detect is valid.
0
The PLL2 VCO tuning algorithm runs immediately after any PLL2_N counter update, despite the state of PLL1
Digital Lock Detect.
If the user is unsure of the state of the reference clock input at startup of the LMK040xx device, setting
RC_DLD1_Start = 0 will allow PLL2 to tune and lock the internal VCO to the oscillator attached to the OSCin
port. This ensures that the active clock outputs will start up at frequencies close to their desired values. The error
in clock output frequency will depend on the open loop accuracy of the oscillator driving the OSCin port. The
frequency of an active clock output is normally given by:
If the open loop frequency accuracy of the external oscillator (either a VCXO or crystal based oscillator) is "X"
ppm, then the error in the output clock frequency (FCLK error) will be:
34
Copyright 2008–2011, Texas Instruments Incorporated
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