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參數(shù)資料
| 型號： | LM25066PSQX |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 電源管理 |
| 英文描述： | POWER SUPPLY SUPPORT CKT, QCC24 |
| 封裝： | LLP-24 |
| 文件頁數(shù)： | 6/48頁 |
| 文件大?。?/td> | 1456K |
| 代理商： | LM25066PSQX |
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FIGURE 2. Power Up Sequence (Current Limit Only)
Gate Control
A charge pump provides the voltage at the GATE pin to en-
hance the N-Channel MOSFET’s gate. During normal oper-
ating conditions (t
by an internal 22 A current source. The voltage at the GATE
pin (with respect to ground) is limited by an internal 18.8 V
zener diode. See the graph “GATE Pin Voltage” shown pre-
viously. Since the gate-to-source voltage applied to Q
1 could
be as high as 18.8 V during various conditions, a zener diode
with the appropriate voltage rating must be added between
the GATE and OUT pins if the maximum V
GS rating of the
selected MOSFET is less than 18.8 V. The external zener
diode must have a forward current rating of at least 190 mA.
When the system voltage is initially applied, the GATE pin is
held low by a 190 mA pull-down current. This helps prevent
an inadvertent turn-on of the MOSFET through its drain-gate
capacitance as the applied system voltage increases.
During the insertion time (t
1 in Figure 2) the GATE pin is held
low by a 2 mA pull-down current. This maintains Q
1 in the off-
state until the end of t
1, regardless of the voltage at VIN or
UVLO. Following the insertion time (t
2 in Figure 2), the gate
voltage of Q
1 is controlled to keep the current or power dissi-
pation level from exceeding the programmed levels. While in
the current or power limiting mode, the TIMER pin capacitor
is charging. If the current and power limiting cease before the
TIMER pin reaches 1.7V, the TIMER pin capacitor then dis-
charges, and the circuit begins normal operation. If the inrush
limiting condition persists such that the TIMER pin reached
1.7V during t
2, the GATE pin is then pulled low by the 190 mA
pull-down current. The GATE pin is then held low until either
a power up sequence is initiated (RETRY pin to VDD), or an
automatic retry is attempted (RETRY pin to GROUND). See
the Fault Timer & Restart section. If the system input voltage
falls below the UVLO threshold or rises above the OVLO
threshold, the GATE pin is pulled low by the 2 mA pull-down
current to switch off Q
1.
Current Limit
The current limit threshold is reached when the voltage across
the sense resistor R
S (VIN to SENSE) exceeds the internal
voltage limit of 25 mV or 46 mV depending on whether the CL
pin is connected to GND or VDD, respectively. In the current
limiting condition, the GATE voltage is controlled to limit the
current in MOSFET Q
1. While the current limit circuit is active,
the fault timer is active as described in the Fault Timer &
Restart section. If the load current falls below the current limit
threshold before the end of the Fault Timeout Period, the
LM25066 resumes normal operation. If the current limit con-
dition persists for longer than the Fault Timeout Period set by
the timer capacitor, C
T, the IIN OC FAULT bit in the
www.national.com
14
LM25066
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