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參數(shù)資料
| 型號： | LM25066PSQX |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 電源管理 |
| 英文描述： | POWER SUPPLY SUPPORT CKT, QCC24 |
| 封裝： | LLP-24 |
| 文件頁數(shù)： | 5/48頁 |
| 文件大?。?/td> | 1456K |
| 代理商： | LM25066PSQX |
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FIGURE 1. Typical Application Circuit
Power Up Sequence
The VIN operating range of the LM25066 is +2.9V to +17V,
with transient capability to +24V. Referring to Figure 1 and
Figure 2, as the voltage at VIN initially increases, the external
N-channel MOSFET (Q
1) is held off by an internal 190 mA
pull-down current at the GATE pin. The strong pull-down cur-
rent at the GATE pin prevents an inadvertent turn-on as the
MOSFET’s gate-to-drain (Miller) capacitance is charged. Ad-
ditionally, the TIMER pin is initially held at ground. When the
V
IN voltage reaches the POR threshold, the insertion time be-
gins. During the insertion time, the capacitor at the TIMER pin
(C
T) is charged by a 5.5 A current source and Q1 is held off
by a 2 mA pull-down current at the GATE pin regardless of
the input voltage. The insertion time delay allows ringing and
transients at VIN to settle before Q
1 is enabled. The insertion
time ends when the TIMER pin voltage reaches 1.7V. C
T is
then quickly discharged by an internal 1.9 mA pull-down cur-
rent. The GATE pin then switches on Q
1 when VSYS, the input
supply voltage, exceeds the UVLO threshold. If V
SYS is above
the UVLO threshold at the end of the insertion time, Q
1 switch-
es on at that time. The GATE pin charge pump sources 22 A
to charge the gate capacitance of Q
1. The maximum voltage
at the GATE pin with respect to ground is limited by an internal
18.8V zener diode.
As the voltage at the OUT pin increases, the LM25066 mon-
itors the drain current and power dissipation of MOSFET Q
1.
Inrush current limiting and/or power limiting circuits actively
control the current delivered to the load. During the inrush
limiting interval (t
2 in Figure 2), an internal 90 A fault timer
current source charges C
T. If Q1’s power dissipation and the
input current reduce below their respective limiting thresholds
before the TIMER pin reaches 1.7V, the 90 A current source
is switched off and C
T is discharged by the internal 2.8 A
current sink (t
3 in Figure 2). The PGD pin switches high when
FB exceeds its rising threshold of 1.167V.
If the TIMER pin voltage reaches 1.7V before inrush current
limiting or power limiting ceases during t
2, a fault is declared
and Q
1 is turned off. See the Fault Timer & Restart section for
a complete description of the fault mode.
The LM25066 will pull the SMBA pin low after the input voltage
has exceeded its POR threshold to indicate that the volatile
memory and device settings are in their default state. The
CONFIG_PRESET bit within the STATUS_MFR_SPECIFIC
register (80h) indicates default configuration of warning
thresholds and device operation and will remain set until a
CLEAR_FAULTS command is received.
13
www.national.com
LM25066
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