參數(shù)資料
型號: LM25066PSQX
廠商: NATIONAL SEMICONDUCTOR CORP
元件分類: 電源管理
英文描述: POWER SUPPLY SUPPORT CKT, QCC24
封裝: LLP-24
文件頁數(shù): 13/48頁
文件大?。?/td> 1456K
代理商: LM25066PSQX
the regulated current is at a minimum. The voltage across the
sense resistor during power limit can be expressed as follows:
(3)
where I
L is the current in RS and VDS is the voltage across
Q
1. For example, if the power limit is set at 20W with RS = 10
m
and V
DS = 15V, the sense resistor voltage calculates to
13.3 mV, which is comfortably regulated by the LM25066.
However, if the power limit is set lower (e.g. 2W), the sense
resistor voltage calculates to 1.33 mV. At this low level, noise
and offsets within the LM25066 may degrade the power limit
accuracy. To maintain accuracy, the sense resistor voltage
should not be less than 5 mV.
TURN-ON TIME
The output turn-on time depends on whether the LM25066
operates in current limit, or in both power limit and current
limit, during turn-on.
A) Turn-on with current limit only:
The current limit thresh-
old (I
LIM) is determined by the current sense resistor (RS). If
the current limit threshold is less than the current defined by
the power limit threshold at maximum V
DS, the circuit operates
at the current limit threshold only during turn-on. Referring to
Figure 8A, as the load current reaches I
LIM, the gate-to-source
voltage is controlled at V
GSL to maintain the current at ILIM. As
the output voltage reaches its final value (V
DS 0V) the drain
current reduces to its normal operating value. The time for the
OUT pin voltage to transition from zero volts to V
SYS is equal
to:
(4)
where C
L is the load capacitance. For example, if VSYS = 12V,
C
L = 1000 F, and ILIM = 1A, tON calculates to 12 ms. The
maximum instantaneous power dissipated in the MOSFET is
12W. This calculation assumes the time from t
1 to t2 in Figure
9(a) is small compared to t
ON and the load does not draw any
current until after the output voltage has reached its final val-
ue, and PGD switches high (Figure 8A). The Fault Timeout
Period must be set longer than t
ON to prevent a fault shutdown
before the turn-on sequence is complete.
If the load draws current during the turn-on sequence (Figure
8B), the turn-on time is longer than the above calculation and
is approximately equal to:
(5)
where R
L is the load resistance. The Fault Timeout Period
must be set longer than t
ON to prevent a fault shutdown before
the turn-on sequence is complete.
30115822
A. No Load Current During Turn-On
30115823
B. Load Draws Current During Turn-On
FIGURE 8.
B) Turn-On with Power Limit and Current Limit:
The max-
imum allowed power dissipation in Q
1 (PMOSFET(LIM)) is de-
fined by the resistor at the PWR pin, and the current sense
resistor R
S. See the Power Limit Threshold section. If the cur-
rent limit threshold (I
LIM) is higher than the current defined by
the power limit threshold at maximum V
DS (PMOSFET(LIM)/
V
SYS), the circuit operates initially in the power limit mode
when the V
DS of Q1 is high and then transitions to current limit
mode as the current increases to I
LIM and VDS decreases. As-
suming the load (R
L) is not connected during turn-on, the time
for the output voltage to reach its final value is approximately
equal to:
(6)
For example, if V
SYS = 12V, CL = 1000 F, ILIM = 1A, and
P
MOSFET(LIM) = 10W, tON calculates to 12.2 ms, and the initial
current level (I
P) is approximately 0.83A. The Fault Timeout
Period must be set longer than t
ON.
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LM25066
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