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參數(shù)資料
| 型號： | LM25066PSQX |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 電源管理 |
| 英文描述： | POWER SUPPLY SUPPORT CKT, QCC24 |
| 封裝： | LLP-24 |
| 文件頁數(shù)： | 17/48頁 |
| 文件大小： | 1456K |
| 代理商： | LM25066PSQX |
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Option D:
The OVLO function can be disabled by grounding
the OVLO pin. The UVLO thresholds are set as described in
Option B or Option C.
POWER GOOD
When the voltage at the FB pin increases above its threshold,
the internal pull-down acting on the PGD pin is disabled al-
lowing PGD to rise to V
PGD through the pull-up resistor, RPG,
as shown in Figure 14. The pull-up voltage (V
PGD) can be as
high as 17V, and can be higher or lower than the voltages at
VIN and OUT. VDD is a convenient choice for V
PGD as it al-
lows interface to low voltage logic and avoids glitching on
PGD during power-up. If a delay is required at PGD, suggest-
C
PG adds delay to the rising edge, but not to the falling edge.
In Figure 15B, the rising edge is delayed by R
PG1 + RPG2 and
C
PG, while the falling edge is delayed a lesser amount by
R
lows for equal delays at the two edges, or a short delay at the
rising edge and a long delay at the falling edge.
Setting the output threshold for the PGD pin requires two re-
sistors (R4, R5) as shown in Figure 13 . While monitoring the
output voltage is shown in Figure 13, R4 can be connected to
any other voltage which requires monitoring.
The resistor values are calculated as follows:
Choose the upper and lower threshold (V
PGDH) and (VPGDL)
at V
OUT.
As an example, assume the application requires the following
thresholds: V
PGDH = 10.14V, and VPGDL = 9.9V. Therefore
V
PGD(HYS) = 0.24V. The resistor values are:
R4 = 10 k
, R5 = 1.3 k
Where the R4 and R5 resistor values are known, the threshold
voltages and hysteresis are calculated from the following:
301158a5
FIGURE 13. Programming the PGD Threshold
30115851
FIGURE 14. Power Good Output
www.national.com
24
LM25066
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