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參數(shù)資料
| 型號： | LM25066PSQX |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 電源管理 |
| 英文描述： | POWER SUPPLY SUPPORT CKT, QCC24 |
| 封裝： | LLP-24 |
| 文件頁數(shù)： | 10/48頁 |
| 文件大?。?/td> | 1456K |
| 代理商： | LM25066PSQX |
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Applications Section
30115801
FIGURE 6. Typical Application Circuit
DESIGN-IN PROCEDURE
(Refer to Figure 6 for Typical Application Circuit) Shown here
is the step-by-step procedure for hardware design of the
LM25066. This procedure refers to section numbers that pro-
vide detailed information on the following design steps. The
recommended design-in procedure is as follows:
MOSFET Selection:
Determine MOSFET value based on
breakdown voltage, current and power ratings.
Current Limit, R
S: Determine the current limit threshold
(I
LIM). This threshold must be higher than the normal maxi-
mum load current, allowing for tolerances in the current sense
resistor value and the LM25066 Current Limit threshold volt-
age. Use equation 1 to determine the value for R
S.
Power Limit Threshold:
Determine the maximum allowable
power dissipation for the series pass MOSFET (Q
1) using the
device’s SOA information. Use equation 2 to determine the
value for R
PWR.
Turn-On Time and TIMER Capacitor, C
T: Determine the
value for the timing capacitor at the TIMER pin (C
T) using
equation 8. The fault timeout period (t
FAULT) MUST be longer
than the circuit’s turn-on-time. The turn-on time can be esti-
mated using the equations in the TURN-ON TIME section of
this data sheet, but should be verified experimentally. Review
the resulting insertion time, and the restart timing if retry is
enabled.
UVLO, OVLO:
Choose option A, B, C, or D from the UVLO,
OVLO section of the Application Information to set the UVLO
and OVLO thresholds and hysteresis. Use the procedure for
the appropriate option to determine the resistor values at the
UVLO/EN and OVLO pins.
Power Good:
Choose the appropriate output voltage and
calculate the required resistor divider from the output voltage
to the FB pin. Choose either VDD or OUT to connect properly
sized pull-up resistor for the Power Good output (PGD).
Refer to Programming Guide section:
After all hardware
design is complete, refer to the programming guide for a step
by step procedure regarding software.
MOSFET SELECTION
It is recommended that the external MOSFET (Q
1) selection
be based on the following criteria:
- The BV
DSS rating should be greater than the maximum sys-
tem voltage (V
SYS), plus ringing and transients which can
occur at V
SYS when the circuit card, or adjacent cards, are
inserted or removed.
- The maximum continuous current rating should be based on
the current limit threshold (e.g. 25 mV/R
S), not the maximum
load current, since the circuit can operate near the current
limit threshold continuously.
- The Pulsed Drain Current spec (I
DM) must be greater than
the current threshold for the circuit breaker function (45 mV/
R
S when CL = CB = GND).
- The SOA (Safe Operating Area) chart of the device and its
thermal properties should be used to determine the maximum
power dissipation threshold set by the R
PWR resistor. The
programmed maximum power dissipation should have a rea-
sonable margin from the maximum power defined by the
MOSFET’s SOA curve (if the device is set to infinitely retry,
the MOSFET will be repeatedly stressed during fault restart
www.national.com
18
LM25066
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