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參數(shù)資料
| 型號： | LM25066PSQX |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 電源管理 |
| 英文描述： | POWER SUPPLY SUPPORT CKT, QCC24 |
| 封裝： | LLP-24 |
| 文件頁數(shù)： | 14/48頁 |
| 文件大?。?/td> | 1456K |
| 代理商： | LM25066PSQX |
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30115825
FIGURE 9. MOSFET Power Up Waveforms
TIMER CAPACITOR, C
T
The TIMER pin capacitor (C
T) sets the timing for the insertion
time delay, fault timeout period, and the restart timing of the
LM25066.
A) Insertion Delay -
Upon applying the system voltage
(V
SYS) to the circuit, the external MOSFET (Q1) is held off
during the insertion time (t
1 in Figure 2) to allow ringing and
transients at V
SYS to settle. Since each backplane’s response
to a circuit card plug-in is unique, the worst case settling time
must be determined for each application. The insertion time
starts when VIN reaches the POR threshold, at which time the
internal 5.5 A current source charges C
T from 0V to 1.7V.
The required capacitor value is calculated from:
(7)
For example, if the desired insertion delay is 250 ms, C
T cal-
culates to 0.8 F. At the end of the insertion delay, C
T is
quickly discharged by a 1.9 mA current sink.
B) Fault Timeout Period -
During inrush current limiting or
upon detection of a fault condition where the current limit and/
or power limit circuits regulate the current through Q
1, the fault
timer current source (90 A) is switched on to charge C
T. The
Fault Timeout Period is the time required for the TIMER pin
voltage to reach 1.7V, at which time Q
1 is switched off. The
required capacitor value for the desired Fault Timeout Period
t
FAULT is calculated from:
(8)
For example, if the desired Fault Timeout Period is 15 ms,
C
T calculates to 0.8 F. CT is discharged by the 2.8 A current
sink at the end of the Fault Timeout Period. After the Fault
Timeout Period, if retry is disabled, the LM25066 latches the
GATE pin low until a power up sequence is initiated by exter-
nal circuitry. When the Fault Timeout Period of the LM25066
expires, a restart sequence starts as described below
(Restart Timing). During consecutive cycles of the restart se-
quence, the fault timeout period is shorter than the initial fault
timeout period described above by approximately 20% since
the voltage at the TIMER pin starts ramping up from 0.3V
rather than ground.
Since the LM25066 normally operates in power limit and/or
current limit during a power up sequence, the Fault Timeout
Period MUST be longer than the time required for the output
voltage to reach its final value. See the Turn-On Time section.
C) Restart Timing
- For the LM25066, after the Fault Timeout
Period described above, C
T is discharged by the 2.8 A cur-
rent sink to 1V. The TIMER pin then cycles through seven
additional charge/discharge cycles between 1V and 1.7V as
shown in Figure 4. The restart time ends when the TIMER pin
voltage reaches 0.3V during the final high-to-low ramp. The
restart time, after the Fault Timeout Period, is equal to:
(9)
= C
T x 2.3 x 10
6
(10)
For example, if C
T = 0.8 F, tRESTART = 2 seconds. At the end
of the restart time, Q
1 is switched on. If the fault is still present,
the fault timeout and restart sequence repeats. The on-time
duty cycle of Q
1 is approximately 0.67% in this mode.
UVLO, OVLO
By programming the UVLO and OVLO thresholds the
LM25066 enables the series pass device (Q
1) when the input
supply voltage (V
SYS) is within the desired operational range.
If V
SYS is below the UVLO threshold, or above the OVLO
threshold, Q
1 is switched off, denying power to the load. Hys-
teresis is provided for each threshold.
Option A:
The configuration shown in Figure 10 requires
three resistors (R1-R3) to set the thresholds.
21
www.national.com
LM25066
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