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參數(shù)資料
| 型號： | LM25066APSQE |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 電源管理 |
| 英文描述： | POWER SUPPLY SUPPORT CKT, QCC24 |
| 封裝： | LLP-24 |
| 文件頁數(shù)： | 7/48頁 |
| 文件大?。?/td> | 1658K |
| 代理商： | LM25066APSQE |
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STATUS_INPUT (7Ch) register, the INPUT bit in the
STATUS_WORD
(79h)
register,
and
the
IIN_OC/
PFET_OP_FAULT bit in the DIAGNOSTIC_WORD (E1h)
register will all be toggled high, and SMBA pin will be pulled
low unless this feature is disabled using the ALERT_MASK
(D8h) register. For proper operation, the R
S resistor value
should be less than 200 m
. Higher values may create in-
stability in the current limit control loop. The current limit
threshold pin value may be overridden by setting appropriate
bits in the DEVICE_SETUP register (D9h).
Circuit Breaker
If the load current increases rapidly (e.g. the load is short cir-
cuited), the current in the sense resistor (R
S) may exceed the
current limit threshold before the current limit control loop is
able to respond. If the current exceeds 1.8 or 3.6 times (user
settable) the current limit threshold, Q
1 is quickly switched off
by the 190 mA pull-down current at the GATE pin and a Fault
Timeout Period begins. When the voltage across R
S falls be-
low the threshold, the 190 mA pull-down current at the GATE
pin is switched off and the gate voltage of Q
1 is then deter-
mined by the current limit or power limit functions. If the
TIMER pin reaches 1.7V before the current limiting or power
limiting condition ceases, Q
1 is switched off by the 2 mA pull-
down current at the GATE pin as described in the Fault Timer
& Restart section. A circuit breaker event will cause the
CIRCUIT_BREAKER_FAULT bit in the STATUS_MFR_SPE-
CIFIC (80h) and DIAGNOSTIC_WORD (E1h) registers to be
toggled high and SMBA pin will be pulled low unless this fea-
ture is disabled using the ALERT_MASK (D8h) register. The
circuit breaker pin configuration may be overridden by setting
appropriate bits in the DEVICE_SETUP (D9h) register.
Power Limit
An important feature of the LM25066A is the MOSFET power
limiting. The Power Limit function can be used to maintain the
maximum power dissipation of MOSFET Q
1 within the device
SOA rating. The LM25066A determines the power dissipation
in Q
1 by monitoring its drain-source voltage (SENSE to OUT),
and the drain current through R
S (VIN to SENSE). The prod-
uct of the current and voltage is compared to the power limit
threshold programmed by the resistor at the PWR pin. If the
power dissipation reaches the limiting threshold, the GATE
voltage is controlled to regulate the current in Q
1. While the
power limiting circuit is active, the fault timer is active as de-
scribed in the Fault Timer & Restart section. If the power limit
condition persists for longer than the Fault Timeout Period set
by the timer capacitor, C
T, the IIN OC FAULT bit in the
STATUS_INPUT (7Ch) register, the INPUT bit in the
STATUS_WORD
(79h)
register,
and
the
IIN_OC/
PFET_OP_FAULT bit in the DIAGNOSTIC_WORD (E1h)
register will all be toggled high, and SMBA pin will be pulled
low unless this feature is disabled using the ALERT_MASK
(D8h) register.
Fault Timer & Restart
When the current limit or power limit threshold is reached
during turn-on, or as a result of a fault condition, the gate-to-
source voltage of Q
1 is controlled to regulate the load current
and power dissipation in Q
1. When either limiting function is
active, a 90 A fault timer current source charges the external
capacitor (C
T) at the TIMER pin as shown in Figure 4 (Fault
Timeout Period). If the fault condition subsides during the
Fault Timeout Period before the TIMER pin reaches 1.7V, the
LM25066A returns to the normal operating mode and C
T is
discharged by the 1.9 mA current sink. If the TIMER pin
reaches 1.7V during the Fault Timeout Period, Q
1 is switched
off by a 2 mA pull-down current at the GATE pin. The subse-
quent restart procedure then depends on the selected retry
configuration.
If the RETRY pin is high, the LM25066A latches the GATE
pin low at the end of the Fault Timeout Period. C
T is then dis-
charged to ground by the 2.8 A fault current sink. The GATE
pin is held low by the 2 mA pull-down current until a power up
sequence is externally initiated by cycling the input voltage
(V
SYS), or momentarily pulling the UVLO/EN pin below its
threshold with an open-collector or open-drain device as
shown in Figure 3. The voltage at the TIMER pin must be
<0.3V for the restart procedure to be effective. The
TIMER_LATCHED_OFF bit in the DIAGNOSTIC_WORD
(E1h) register will remain high while the latched off condition
persists.
30146015
FIGURE 3. Latched Fault Restart Control
The LM25066A provides an automatic restart sequence
which consists of the TIMER pin cycling between 1.7V and
1V seven times after the Fault Timeout Period, as shown in
Figure 4. The period of each cycle is determined by the 90 A
charging current, and the 2.8 A discharge current, and the
value of the capacitor C
T. When the TIMER pin reaches 0.3V
during the eighth high-to-low ramp, the 22 A current source
at the GATE pin turns on Q
1. If the fault condition is still
present, the Fault Timeout Period and the restart sequence
repeat. The RETRY pin allows selecting no retries or infinite
retries. Finer control of the retry behavior can be achieved
through the DEVICE_SETUP (D9h) register. Retry counts of
0, 1, 2, 4, 8, 16 or infinite may be selected by setting the ap-
propriate bits in the DEVICE_SETUP (D9h) register.
15
www.national.com
LM25066A
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| LM25066APSQE/NOPB | 功能描述:熱插拔功率分布 RoHS:否 制造商:Texas Instruments 產(chǎn)品:Controllers & Switches 電流限制: 電源電壓-最大:7 V 電源電壓-最小:- 0.3 V 工作溫度范圍: 功率耗散: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MSOP-8 封裝:Tube |
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| LM25066IAPSQ/NOPB | 制造商:Texas Instruments 功能描述:IC PWR MGMT/PROT PMBUS 24WQFN 制造商:Texas Instruments 功能描述:System PWR Mgmt & Protection IC |
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