參數(shù)資料
型號(hào)： LM25066APSQE
廠商： NATIONAL SEMICONDUCTOR CORP
元件分類： 電源管理
英文描述： POWER SUPPLY SUPPORT CKT, QCC24
封裝： LLP-24
文件頁(yè)數(shù)： 34/48頁(yè)
文件大?。?/td> 1658K
代理商： LM25066APSQE
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
VIN, SENSE to GND (Note 6)
-0.3V to 24V
GATE, FB, UVLO/EN, OVLO, PGD,
OUT to GND (Note 6)
-0.3V to 20V
SCL, SDA, SMBA, CL, CB, ADR0,
ADR1, ADR2, VDD, VAUX, DIODE,
RETRY to GND
-0.3V to 6V
VIN to SENSE
-0.3V to +0.3V
ESD Rating (Note 2)
Human Body Model
2kV
Storage Temperature
-65°C to +150°C
Junction Temperature
+150°C
Operating Ratings
VIN, SENSE, OUT voltage
2.9V to 17V
VDD
2.9V to 5.5V
Junction Temperature
40°C to +125°C
Electrical Characteristics Limits in standard type are for T
J = 25°C only; limits in boldface type apply over the
junction temperature (T
J) range of -40°C to +85°C unless otherwise stated. Minimum and Maximum limits are guaranteed through
test, design, or statistical correlation. Typical values represent the most likely parametric norm at T
J = 25°C, and are provided for
reference purposes only. Unless otherwise stated the following conditions apply: VIN = 12V. See (Note 3) and (Note 7).
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Units
Input (VIN Pin)
I
IN-EN
Input Current, enabled
UVLO = 2V and OVLO = 0.7V
5.8
8
mA
POR
Power On Reset threshold at VIN
VIN increasing
2.6
2.8
V
POR
HYS
POR
EN Hysteresis
VIN decreasing
150
mV
VDD Regulator (VDD pin)
V
DD
I
VDD = 5mA, VIN = 12V
4.3
4.5
4.7
V
I
VDD = 5mA, VIN = 4.5V
3.5
3.9
4.3
V
DDILIM
VDD Current Limit
25
45
mA
UVLO/EN, OVLO Pins
UVLO
TH
UVLO threshold
V
UVLO falling
1.147
1.16
1.173
V
UVLO
HYS
UVLO hysteresis current
UVLO = 1V
18
23
28
A
UVLO
DEL
UVLO delay
Delay to GATE high
8
s
Delay to GATE low
20
UVLO
BIAS
UVLO bias current
UVLO = 3V
1
A
OVLO
TH
OVLO threshold
V
OVLO rising
1.141
1.16
1.185
V
OVLO
HYS
OVLO hysteresis current
OVLO = 1V
-28
-23
-18
A
OVLO
DEL
OVLO delay
Delay to GATE high
19
s
Delay to GATE low
9
OVLO
BIAS
OVLO bias current
OVLO = 1V
1
A
Power Good (PGD pin)
PGD
VOL
Output low voltage
I
SINK = 2 mA
25
60
mV
PGD
IOH
Off leakage current
V
PGD = 17V
1
A
PGD
DELAY
Power Good Delay
V
FB to VPG
115
ns
FB Pin
FB
TH
FB Threshold
V
FB rising
1.141
1.167
1.19
V
FB
HYS
FB Hysteresis Current
-31
-24
-18
A
FB
LEAK
Off Leakage Current
V
FB = 1V
1
A
Power Limit (PWR Pin)
PWR
LIM
Power limit sense voltage (VIN-SENSE) SENSE-OUT = 12V, R
PWR = 25 k
9
12.5
15
mV
I
PWR
PWR pin current
V
PWR = 2.5V
-10
A
R
SAT(PWR)
PWR pin impedance when disabled
UVLO = 0.7V
180
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LM25066A
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